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Intel
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IXP42X product line and IXC1100 control plane processors—Intel XScale
®
Processor
Intel
®
IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
DM September 2006
116 Order Number: 252480-006US
3.6.14 Downloading Code in ICache
On IXP42X product line and IXC1100 control plane processors, a 2-K mini instruction
cache — physically separate from the 32-K main instruction cache — can be used as an
on-chip instruction RAM. An external host can download code directly into either
instruction cache through JTAG. In addition to downloading code, several cache
functions are supported.
Note: A cache line fill from external memory will never be written into the mini-instruction
cache. The only way to load a line into the mini-instruction cache is through JTAG.
The IXP42X product line and IXC1100 control plane processors support loading the
instruction cache during reset and during program execution. Loading the instruction
cache during normal program execution requires a strict handshaking protocol between
software running on the IXP42X product line and IXC1100 control plane processors and
the external host.
In the remainder of this section the term ‘instruction cache’ applies to either main or
mini instruction cache.
3.6.14.1 LDIC JTAG Command
The LDIC JTAG instruction selects the JTAG data register for loading code into the
instruction cache. The JTAG op code for this instruction is ‘00111’. The LDIC instruction
must be in the JTAG instruction register in order to load code directly into the
instruction cache through JTAG.