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Intel
®
IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
September 2006 DM
Order Number: 252480-006US 511
Universal Serial Bus (USB) v1.1 Device Controller—Intel
®
IXP42X product line and IXC1100
control plane processors
The bit’s read value is zero.
18.5.15.4 Transmit Underrun (TUR)
The transmit underrun bit is be set if the transmit FIFO experiences an underrun. When
the UDC experiences an underrun, UDCCS13[TUR] generates an interrupt.
UDCCS13[TUR] is cleared by writing a 1 to it.
18.5.15.5 Bit 4 Reserved
Bit 4 is reserved for future use.
18.5.15.6 Bit 5 Reserved
Bit 5 is reserved for future use.
18.5.15.7 Bit 6 Reserved
Bit 6 is reserved for future use.
18.5.15.8 Transmit Short Packet (TSP)
Software uses the transmit short packet to indicate that the last byte of a data transfer
has been sent to the FIFO. This indicates to the UDC that a short packet or zero-sized
packet is ready to transmit.
Software must not set this bit, if a packet of 256 bytes is to be transmitted. When the
data packet is successfully transmitted, this bit is cleared by the UDC.
Register Name: UDCCS13
Hex Offset Address: 0 x C800 B044 Reset Hex Value: 0 x 00000001
Register
Description:
Register Description: Universal Serial Bus Device Controller Endpoint 13 Control and Status Register
Access: Read/Write
Bits
31 876543210
(Reserved)
TSP
(Rsvd)
(Rsvd)
(Rsvd)
TUR
FTF
TPC
TFS
00000001
Resets (Above)
Register
UDCCS13 (Sheet 1 of 2)
Bits Name Description
31:8 Reserved for future use.
7TSP
Transmit short packet (read/write 1 to set).
1 = Short packet ready for transmission.
6 (Reserved). Always reads 0.
5 (Reserved). Always reads 0.
4 (Reserved). Always reads 0.