Filter
Top Products
Intel
®
IXP42X product line and IXC1100 control plane processors—PCI Controller
Intel
®
IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
DM September 2006
242 Order Number: 252480-006US
Bit 4 (AHB Big-endian Addressing Mode) defines to the PCI Controller how the data
being sent to and from the AHB master and target interfaces are addressed. Figure 47
through Figure 52 shows the various configurations and the values returned from the
PCI Controller when the AHB Master and Target Interfaces are configured in both big
endian and little endian mode of operation. It is stressed that the PCI Controller will not
function properly if bit 4 is set to little-endian address mode (logic 0). Big-endian
mode of operation must always be used and this bit should be the first bit set in the PCI
Controller initialization process.
As shown in Figure 47, when an external PCI device accesses an AHB address using the
PCI Controller Target Interface with the South AHB configured in big-endian mode of
operation (Bit 4 (AHB Big-endian Addressing Mode) of the PCI Controller Control and
Status Register set to logic 1) and the PCI Target Transfer Byte Swap (Bit 3 of the PCI
Controller Control and Status Register set to logic 1), the data passed between the PCI
Bus and the AHB will be swapped.
When an external PCI device accesses an AHB address using the PCI Controller Target
Interface with the South AHB configured in big-endian mode of operation 4 (Bit 4 (AHB
Big-endian Addressing Mode) of the PCI Controller Control and Status Register set to
logic 1) and the PCI Target Transfer Byte Swap (Bit 3 of the PCI Controller Control and
Status Register) set to logic 0, the data passed between the PCI Bus and the AHB will
not be swapped. In the following figures, the PCI bytes are numbered according to the
corresponding PCI byte enables and AHB bytes are numbered according to the
corresponding byte address on the AHB bus.
For example, a PCI write with byte enable 2 asserted, the PCI Target Transfer Byte
Swap (Bit 3 of the PCI Controller Control and Status Register) set to logic 1, and the
AHB Big-endian Addressing Mode set to logic 1 will produce an AHB byte write with AHB
address bits [1:0] = 10b. When the PCI Target Transfer Byte Swap (Bit 3 of the PCI
Controller Control and Status Register) set to logic 0, the PCI write with PCI byte
enable 2 asserted will produce an AHB byte write with AHB address bits [1:0] = 01b.