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Intel
®
IXP42X product line and IXC1100 control plane processors—Intel XScale
®
Processor
Intel
®
IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
DM September 2006
64 Order Number: 252480-006US
If there is no outstanding fill request for that line, the current store request is
placed in the fill buffer and a 32-byte external memory read request is made. If the
pending buffer or fill buffer is full, the Intel XScale processor will stall until an entry
is available.
2. The 32-bytes of data can be returned back to the Intel XScale processor in any
word order, i.e, the eight words in the line can be returned in any order. Note that it
does not matter, for performance reasons, which order the data is returned to the
Intel XScale processor since the store operation has to wait until the entire line is
written into the cache before it can complete.
3. When the entire 32-byte line has returned from external memory, a line is allocated
in the cache, selected by the round-robin pointer. The line to be written into the
cache may replace a valid line previously allocated in the cache. In this case both
dirty bits are examined and if any are set, the four words associated with a dirty bit
that’s asserted will be written back to external memory as a 4 word burst
operation. This write operation will be placed in the write buffer.
4. The line is written into the cache along with the data associated with the store
operation.
If the above condition for requesting a 32-byte cache line is not met, a write miss will
cause a write request to external memory for the exact data size specified by the store
operation, assuming the write request doesn’t coalesce with another write operation in
the write buffer.
The Intel XScale processor supports write-back caching or write-through caching,
controlled through the MMU page attributes. When write-through caching is specified,
all store operations are written to external memory even if the access hits the cache.
This feature keeps the external memory coherent with the cache, i.e., no dirty bits are
set for this region of memory in the data/mini-data cache. However write through does
not guarantee that the data/mini-data cache is coherent with external memory, which
is dependent on the system level configuration, specifically if the external memory is
shared by another master.
When write-back caching is specified, a store operation that hits the cache will not
generate a write to external memory, thus reducing external memory traffic.
The line replacement algorithm for the data cache is round-robin. Each set in the data
cache has a round-robin pointer that keeps track of the next line (in that set) to
replace. The next line to replace in a set is the next sequential line after the last one
that was just filled. For example, if the line for the last fill was written into way 5-set 2,
the next line to replace for that set would be way 6. None of the other round-robin
pointers for the other sets are affected in this case.
After reset, way 31 is pointed to by the round-robin pointer for all the sets. Once a line
is written into way 31, the round-robin pointer points to the first available way of a set,
beginning with way 0 if no lines have been re-configured as data RAM in that particular
set. Re-configuring lines as data RAM effectively reduces the available lines for cache
updating. For example, if the first three lines of a set were re-configured, the round-
robin pointer would point to the line at way 3 after it rolled over from way 31. Refer to
“Reconfiguring the Data Cache as Data RAM” on page 68 for more details on data RAM.
The mini-data cache follows the same round-robin replacement algorithm as the data
cache except that there are only two lines the round-robin pointer can point to such
that the round-robin pointer always points to the least recently filled line. A least
recently used replacement algorithm is not supported because the purpose of the mini-
data cache is to cache data that exhibits low temporal locality, i.e.,data that is placed
into the mini-data cache is typically modified once and then written back out to
external memory.