Filter
Top Products
Intel
®
IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
September 2006 DM
Order Number: 252480-006US 217
PCI Controller—Intel
®
IXP42X product line and IXC1100 control plane processors
memory transactions with no adverse side effects to reads. Only bits (31:26) would
be written.
Now, the IXP42X product line and IXC1100 control plane processors must read
Base Address Register 0 to determine the Address Space, Address space type
(memory or I/O), and any limitations to reading this address space.
6. Write a hexadecimal value of 0x00010010 to the PCI Non-Pre-fetch Access Address
(PCI_NP_AD) Register.
This value will allow a read from a Type 0 PCI configuration space address location
0x10. Notice also that address bit 16 is set to logic 1.
This bit is set assuming that ID_SEL for a given device on the local segment is
selected, using address bit 16. This device is the one that is attempting to be
accessed.
7. Write a hexadecimal value of 0x0000000A to the PCI Non-Pre-fetch Access
Command/Byte Enables (PCI_NP_CBE) Register.
Bits 7:4 of this register specify the byte-enables for the data transfer. The selection
of all bits to logic 0 signifies that all bytes are to be read.
Bits 3:0 of this register specify the PCI Command Type to be used for the data
transfer. A logic value of 1010b signifies that a Configuration Read Cycle is being
requested. This action causes the PCI Controller to initiate the read transaction.
8. The data returned will be placed in the PCI Non-Pre-fetch Access Read Data
(PCI_NP_RDATA) Register.
The returned value looks like hexadecimal 0xFC000008. This value signifies that an
address space of 64 Mbyte is being requested by Base Address Register 0 of the
PCI device to be mapped anywhere into the PCI address map, the address space is
a Memory Space, and there are no special read conditions that apply to this
address space. (See the PCI Local Bus Specification, Rev. 2.2 for more details.)
9. Now the IXP42X product line and IXC1100 control plane processors must specify
the PCI address space that this Base Address Register is going to occupy. This is
done by executing a Configuration Write to bits 31:26 of Base Address Register 0 —
with the logical value where the address is going to reside.
Assume we want the address to reside at PCI location 0xA0000000. A Configuration
Write of 0xA0000000 will be written to Base Address Register 0 of the external PCI
device. No other PCI assignment can be placed between PCI addresses
0xA0000000 and 0xA3FFFFFF.
When the IXP42X product line and IXC1100 control plane processors are functioning in
Host mode of operation, all other PCI Configuration Registers contained on external PCI
devices will be configured or used to configure the PCI Bus using PCI Configuration
Read/Write Cycles produced from the IXP42X product line and IXC1100 control plane
processors for each device on the PCI bus. Some examples of these parameters are
Device Identifications, Vendor Identifications, Base Address Register, and Grant
Latencies. (For more details on exact settings/usage of these parameters for a given
application, see the PCI Local Bus Specification, Rev. 2.2.)
The IXP42X product line and IXC1100 control plane processors have now been
successfully configured as a PCI host and successfully configured the PCI bus. PCI
memory and PCI I/O transaction can now take place.
For more detail on generating PCI Memory and PCI I/O transactions using the IXP42X
product line and IXC1100 control plane processors, see “PCI Controller Functioning as
Bus Initiator” on page 226. For more detail on accepting PCI Memory and PCI I/O
transactions using the IXP42X product line and IXC1100 control plane processors, see
“PCI Controller Functioning as Bus Target” on page 234.