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Intel
®
IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
September 2006 DM
Order Number: 252480-006US 267
PCI Controller—Intel
®
IXP42X product line and IXC1100 control plane processors
6.14.2.14 PCI Memory Base Address Register
(PCI_PCIMEMBASE)
6.14.2.15 AHB Doorbell Register
(PCI_AHBDOORBELL)
Register PCI_AHBIOBASE
Bits Name Description
Reset
Value
PCI Access AHB Access
31:2
4
(Reserved) – Read as 0 0x00 RO RO
23:0 Iobase
Upper 24 AHB address bits for PCI accesses that
target pci_bar5.
0x000000 RO RW
Register Name: PCI_PCIMEMBASE
Hex Offset Address: 0xC0000034 Reset Hex Value: 0x00000000
Register
Description:
Provides upper 8 PCI address bits for AHB accesses of PCI memory space. Lower 24 bits of PCI address
provided directly from the AHB bus. Four Membase fields correspond to accesses from the AHB bus that
target specific AHB address ranges.
Access: See below.
31 24 23 16 15 8 7 0
Membase0 Membase1 Membase2 Membase3
Register
PCI_PCIMEMBASE
Bits Name Description
Reset
Value
PCI Access AHB Access
31:2
4
PCIbase0
Upper 8 PCI address bits for AHB accesses that target
the first 16Mbyte PCI memory partition.
0x00 RO RW
23:1
6
PCIbase1
Upper 8 PCI address bits for AHB accesses that target
the second 16Mbyte PCI memory partition.
0x00 RO RW
15:8 PCIbase2
Upper 8 PCI address bits for AHB accesses that target
the third 16Mbyte PCI memory partition.
0x00 RO RW
7:0 PCIbase3
Upper 8 PCI address bits for AHB accesses that target
the fourth 16Mbyte PCI memory partition.
0x00 RO RW
Register Name: PCI_AHBDOORBELL
Hex Offset Address: 0xC0000038 Reset Hex Value: 0x00000000
Register
Description:
An external PCI device writes this register to assert the pcc_int signal to interrupt the Intel XScale
processor. Any bit set to a 1 will assert pcc_int if the AHB doorbell interrupt is enabled (pci_inten.ADBEN
= 1). This register is write-1-to-set from PCI and write-1-to-clear from AHB. The PCI device writes a 1 to
a bit or pattern of bits to generate the interrupt. The AHB agent reads the register and writes 1(s) to
clear the bit(s) and de-assert the interrupt. If the DBT (Doorbell Test) bit is set in the pci_csr register, all
bits become read/write from the AHB bus.
Access: See below.
31 0
ADB