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Intel
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IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
September 2006 DM
Order Number: 252480-006US 51
Intel XScale
®
Processor—Intel
®
IXP42X product line and IXC1100 control plane processors
Note: Care must be exercised here when allowing exceptions to occur during this routine
whose handlers may have data that lies in a page that is trying to be locked into the
TLB.
3.1.3.4 Round-Robin Replacement Algorithm
The line replacement algorithm for the TLBs is round-robin; there is a round-robin
pointer that keeps track of the next entry to replace. The next entry to replace is the
one sequentially after the last entry that was written. For example, if the last virtual to
physical address translation was written into entry 5, the next entry to replace is
entry 6.
At reset, the round-robin pointer is set to entry 31. Once a translation is written into
entry 31, the round-robin pointer gets set to the next available entry, beginning with
entry 0 if no entries have been locked down. Subsequent translations move the round-
robin pointer to the next sequential entry until entry 31 is reached, where it will wrap
back to entry 0 upon the next translation.
A lock pointer is used for locking entries into the TLB and is set to entry 0 at reset. A
TLB lock operation places the specified translation at the entry designated by the lock
pointer, moves the lock pointer to the next sequential entry, and resets the round-robin
pointer to entry 31. Locking entries into either TLB effectively reduces the available
entries for updating. For example, if the first three entries were locked down, the
round-robin pointer would be entry 3 after it rolled over from entry 31.
Example 3. Locking Entries into the Data TLB
; R1, and R2 contain the virtual addresses to translate and lock into the data TLB
MCR P15,0,R1,C8,C6,1 ; Invalidate the data TLB entry specified by the
; virtual address in R1
MCR P15,0,R1,C10,C8,0 ; Translate virtual address (R1) and lock into
; data TLB
; Repeat sequence for virtual address in R2
MCR P15,0,R2,C8,C6,1 ; Invalidate the data TLB entry specified by the
; virtual address in R2
MCR P15,0,R2,C10,C8,0 ; Translate virtual address (R2) and lock into
; data TLB
CPWAIT ; wait for locks to complete
; The MMU is guaranteed to be updated at this point; the next instruction will
; see the locked data TLB entries.