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Intel
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IXP42X product line and IXC1100 control plane processors—Intel XScale
®
Processor
Intel
®
IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
DM September 2006
124 Order Number: 252480-006US
that line. Failure to invalidate a line prior to writing it may cause unpredictable
operation by the processor.
• When the host completes its download, the host must wait a minimum of 15 TCKs,
then switch the JTAG IR to DBGRX, and complete the handshaking (by scanning in
a value that sets DBG_SR[35]). This clears TXRXCTL[31] and allows the debug
handler code to exit the polling loop. The data scanned into DBG_SR[34:3] is
implementation specific.
• After the handler exits the polling loop, it branches to the downloaded code.
Note that this debug handler stub must reside in the instruction cache and execute out
of the cache while doing the synchronization. The processor should not be doing any
code fetches to external memory while code is being downloaded.
3.6.14.5.1 Dynamic Code Download Synchronization
The following pieces of code are necessary in the debug handler to implement the
synchronization used during dynamic code download. The pieces must be ordered in
the handler as shown below.