Filter
Top Products
Intel
®
IXP42X product line and IXC1100 control plane processors—Intel XScale
®
Processor
Intel
®
IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
DM September 2006
178 Order Number: 252480-006US
3.10.3.2 Bit Field Manipulation
The IXP42X product line and IXC1100 control plane processors shift and logical
operations provide a useful way of manipulating bit fields. Bit field operations can be
optimized as follows:
3.10.3.3 Optimizing the Use of Immediate Values
The IXP42X product line and IXC1100 control plane processors’ MOV or MVN
instruction should be used when loading an immediate (constant) value into a register.
Please refer to the ARM* Architecture Reference Manual for the set of immediate values
that can be used in a MOV or MVN instruction. It is also possible to generate a whole
set of constant values using a combination of MOV, MVN, ORR, BIC, and ADD
instructions. The LDR instruction has the potential of incurring a cache miss in addition
to polluting the data and instruction caches. The code samples below illustrate cases
when a combination of the above instructions can be used to set a register to a
constant value:
Note that it is possible to load any 32-bit value into a register using a sequence of four
instructions.
3.10.3.4 Optimizing Integer Multiply and Divide
Multiplication by an integer constant should be optimized to make use of the shift
operation whenever possible.
;Set the bit number specified by r1 in register r0
mov r2, #1
orr r0, r0, r2, asl r1
;Clear the bit number specified by r1 in register r0
mov r2, #1
bic r0, r0, r2, asl r1
;Extract the bit-value of the bit number specified by r1 of the
;value in r0 storing the value in r0
mov r1, r0, asr r1
and r0, r1, #1
;Extract the higher order 8 bits of the value in r0 storing
;the result in r1
mov r1, r0, lsr #24
;Set the value of r0 to 127
mov r0, #127
;Set the value of r0 to 0xfffffefb.
mvn r0, #260
;Set the value of r0 to 257
mov r0, #1
orr r0, r0, #256
;Set the value of r0 to 0x51f
mov r0, #0x1f
orr r0, r0, #0x500
;Set the value of r0 to 0xf100ffff
mvn r0, #0xff, 16
bic r0, r0, #0xe, 8
; Set the value of r0 to 0x12341234
mov r0, #0x8d, 30
orr r0, r0, #0x1, 20
add r0, r0, r0, LSL #16 ; shifter delay of 1 cycle