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Intel
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IXP42X product line and IXC1100 control plane processors—Expansion Bus Controller
Intel
®
IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
DM September 2006
298 Order Number: 252480-006US
8.5 Expansion Bus Interface Configuration
There are eight registers — called the Timing and Control (EXP_TIMING_CS) Registers
— that define the operating mode for each chip select. When designing with the
Expansion Bus Interface, placing the devices on the correct chip selects is required.
Chip Select 0 through 7 can be configured to operate with devices that require an Intel
or Motorola Micro-Processor style bus accesses. These chip selects can be configured to
operate in a multiplexed or a simplex mode of operation — for either Intel- or Motorola-
style bus accesses. Additionally, Chip Select 4 through 7 can be configured to generate
Texas Instruments* HPI-style bus accesses. The mode of operation (Intel, Motorola, or
TI HPI) is set by bits 15:14 of each Timing and Control (EXP_TIMING_CS) Register.
Table 119 shows the possible settings for the Cycle Type selection using bits 15:14 of
the Timing and Control (EXP_TIMING_CS) Register.
Once the cycle type has been determined, the mode of operation must be set. There
are two configurable modes of operation for each chip select, multiplexed and non-
multiplexed. Bit 4 of the Timing and Control (EXP_TIMING_CS) Registers is used to
select this mode. If bit 4 of the Timing and Control (EXP_TIMING_CS) Register is set to
logic 1, the access mode for that Chip Select is multiplexed. Likewise, if bit 4 of the
Timing and Control (EXP_TIMING_CS) Register is set to logic 0, the access mode for
that Chip Select is non-multiplexed.
Multiplexed and non-multiplexed can imply different operations depending upon the
Cycle Type that is selected. For more information refer to section “Expansion Bus
Interface Access Timing Diagrams” on page 305.
The size of the data bus for each device connected to the expansion bus must be
configured. The data bus size is selected on a per-chip-select basis, allowing the most
flexibility when connecting devices to the expansion bus.
There are two valid selections that can be configured for each data bus size, 8-bit or
16-bit. Bit 0 of each Timing and Control (EXP_TIMING_CS) Register is used to select
the data bus size on a per-chip-select basis. When bit 0 is set to logic 0, the data bus
width for the given chip select will be set to 16-bits. When bit 0 is set to logic 1, the
data bus width for the given chip select will be set to 8-bits.
One special case for the data bus width selection is for chip select 0. Chip select 0 (data
bus width) is selected by the value contained on Expansion Bus Address bit 0 at the de-
assertion of reset. At the de-assertion of reset, Expansion Bus Address bit 0 will be
captured into Timing and Control (EXP_TIMING_CS) Register for Chip Select 0. This
feature allows either an 8-bit or 16-bit flash device to be connected to the Expansion
Bus Interface for a boot device.
Table 119. Expansion Bus Cycle Type Selection
Bit[15:14] CYC_TYPE
00 Configures the Expansion Bus Chip Select (x) for Intel cycles
01 Configures the Expansion Bus Chip Select (x) for Motorola* cycles.
10
Configures the Expansion Bus Chip Select (x) for TI* HPI cycles (Only valid for Chip Select 4
through 7)
11 (Reserved)
Note: (x) Can be 0 through 7.