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Intel
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IXP42X product line and IXC1100 control plane processors—Intel XScale
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Intel
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IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
DM September 2006
142 Order Number: 252480-006US
• Total number of data write-back requests to external memory can be derived solely
with PMN1.
3.7.4.6 Instruction TLB Efficiency Mode
PMN0 totals the number of instructions that were executed, which does not include
instructions that were translated by the instruction TLB and never executed. This can
happen if a branch instruction changes the program flow; the instruction TLB may
translate the next sequential instructions after the branch, before it receives the target
address of the branch.
PMN1 counts the number of instruction TLB table-walks, which occurs when there is a
TLB miss. If the instruction TLB is disabled PMN1 will not increment.
Statistics derived from these two events:
• Instruction TLB miss-rate. This is derived by dividing PMN1 by PMN0.
• The average number of cycles it took to execute an instruction or commonly
referred to as cycles-per-instruction (CPI). CPI can be derived by dividing CCNT by
PMN0, where CCNT was used to measure total execution time.
3.7.4.7 Data TLB Efficiency Mode
PMN0 totals the number of data cache accesses, which includes cacheable and non-
cacheable accesses, mini-data cache access and accesses made to locations configured
as data RAM.
Note that STM and LDM will each count as several accesses to the data TLB depending
on the number of registers specified in the register list. LDRD will register two
accesses.
PMN1 counts the number of data TLB table-walks, which occurs when there is a TLB
miss. If the data TLB is disabled PMN1 will not increment.
The statistic derived from these two events is:
Data TLB miss-rate. This is derived by dividing PMN1 by PMN0.
3.7.5 Multiple Performance Monitoring Run Statistics
There may be times when more than four events need to be monitored for performance
tuning. In this case, multiple performance monitoring runs can be done, capturing
different events from each run. For example, the first run could monitor the events
associated with instruction cache performance and the second run could monitor the
events associated with data cache performance. By combining the results, statistics like
total number of memory requests could be derived.
3.7.6 Examples
In this example, the events selected with the Instruction Cache Efficiency mode are
monitored and CCNT is used to measure total execution time. Sampling time ends
when PMN0 overflows which will generate an IRQ interrupt.