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Intel
®
IXP42X product line and IXC1100 control plane processors—Universal Serial Bus (USB)
v1.1 Device Controller
Intel
®
IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
DM September 2006
514 Order Number: 252480-006US
18.5.17 UDC Endpoint 15 Control/Status Register (UDCCS15)
The UDC Endpoint 15 Control Status Register contains six bits that are used to operate
endpoint 15, an Interrupt IN endpoint.
18.5.17.1 Transmit FIFO Service (TFS)
The transmit FIFO service bit is set if the FIFO does not contain any data bytes and
UDCCS15[TSP] is not set.
18.5.17.2 Transmit Packet Complete (TPC)
The transmit packet complete bit is be set by the UDC when an entire packet is sent to
the host. When this bit is set, the IR15 bit in the appropriate UDC status/interrupt
register is set if transmit interrupts are enabled.
This bit can be used to validate the other status/error bits in the Endpoint 15 Control/
Status Register.
The UDCCS15[TPC] bit is cleared by writing a 1 to it. This clears the interrupt source for
the IR15 bit in the appropriate UDC status/interrupt register, but the IR15 bit must also
be cleared.
The UDC issues NAK handshakes to all IN tokens if this bit is set and the buffer is not
triggered by writing 8 bytes or setting UDCCS15[TSP].
18.5.17.3 Flush Tx FIFO (FTF)
The Flush Tx FIFO bit triggers a reset for the endpoint's transmit FIFO. The Flush Tx
FIFO bit is set when software writes a 1 to it or when the host performs a
SET_CONFIGURATION or SET_INTERFACE.
The bit’s read value is 0.
18.5.17.4 Transmit Underrun (TUR)
The transmit underrun bit is be set if the transmit FIFO experiences an underrun. When
the UDC experiences an underrun, NAK handshakes are sent to the host.
UDCCS15[TUR] does not generate an interrupt and is for status only.
UDCCS15[TUR] is cleared by writing a 1 to it.
2ROF
Receive overflow (read/write 1 to clear).
1 = Isochronous data packets are being dropped from the host because the
receiver is full.
1RPC
Receive packet complete (read/write 1 to clear).
0 = Error/status bits invalid.
1= Receive packet has been received and error/status bits are valid.
0RFS
Receive FIFO service (read-only).
0 = Receive FIFO has less than one data packet.
1 = Receive FIFO has one or more data packets.
Register
UDCCS14 (Sheet 2 of 2)
Bits Name Description