Filter
Top Products
Intel
®
IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
September 2006 DM
Order Number: 252480-006US 453
High-Speed Serial Interfaces—Intel
®
IXP42X product line and IXC1100 control plane
processors
Either an internal or external frame-sync pulse or clock can still be utilized. When using
the internal frame-sync pulse/clock, the transmit frame-sync pulse/clock is internally
looped to the receive side of the HSS interface. If an external frame pulse/clock is
used, the clock/frame-sync pulse must be supplied on the transmit frame-sync pulse/
clock pins. The value contained on the transmit frame-sync pulse/clock pins is then
replicated to the receive logic. No data is required to be supplied on any of the receive
signals. This requirement also means that no data is sent or received to or from the
external devices while in loop back mode. The Intel XScale processor — using Intel-
supplied APIs — can be used to activate the loop-back mode.
All of the configuration parameters are predicated on the implementation in the
Network Processor Engine (NPE). For details on exact supported configurations and
protocols using the HSS interface, see the Intel
®
IXP400 Software Programmer’s
Guide.
17.4 Obtaining High-Speed, Serial Synchronization
Before the High-Speed Serial Interface indicates to the Network Processor Engine that
it has receive data, the HSS interface must synchronize to the frame-sync signal.
Receive synchronization must be obtained before any data is placed into the receive
FIFOs.
As stated previously, the Intel APIs and Intel XScale processor can program an offset
between the frame pulse and the start of the frame. This offset will influence the
synchronization process. When there is no offset defined, the HSS interface will be
required to receive two valid frame-sync pulses before synchronization is achieved.
When there is an offset defined, the HSS interface will be required to receive three valid
frame-sync pulses before synchronization is achieved.
If no offset is defined, the first time slot of the second frame will be considered a valid
frame. If an offset is defined, the first time slot of the third frame will be considered a
valid frame. In either case, due to the synchronization protocol the first data the NPE
receives will begin at the start of a frame, thus eliminating the need for time slot
counters.
Conversely, the HSS interface will not request for data from the NPE until the HSS
interface has synced to the transmit frame-sync pulse. The synchronization process is
defined the same as for the receive side. Once transmit synchronization has been
achieved, data will be sent from the NPE to the FIFOs and transmitted over the HSS
interface at the start of the next frame.
If an offset is programmed, the data transmitted over the HSS interface will be
transmitted the offset number of clock cycles before the frame-pulse detection/
generation.
If the HSS Core has not synchronized to the frame-sync pulse, the HSS interface will
remain in an idle state. Data received before synchronization is acquired will be
dropped. When synchronization is not achieved, the transmit data output is set to high
impedance.
If FIFO under-run/over-run occurs, frame synchronization is maintained if the frame-
sync pulses are still generated.
The HSS interface supports “gapped” frame pulses meaning that only an out position
frame pulse will cause a loss of synchronization. A missing frame pulse will not
necessarily cause loss of synchronization to occur.