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Intel
®
IXP42X product line and IXC1100 control plane processors—Universal Asynchronous
Receiver Transceiver (UART)
Intel
®
IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
DM September 2006
358 Order Number: 252480-006US
10.5.1.1 Receive Buffer Register
10.5.1.2 Transmit Holding Register
0x C8001014 0/1 R LSR Line Status Register
0x C8001018 0/1 R MSR Modem Status Register
0x C800101C 0/1 R/W SPR Scratch Pad Register
0x C8001020 0 R/W ISR Slow Infrared Select Register
Register Name: RBR
Hex Offset Address: 0xC800 1000 Reset Hex Value: 0x00000000
Register
Description:
Receive Buffer Register
Access: Read Only.
31 87 0
(Reserved) RBR
Register
RBR
Bits Name Description
31:8 (Reserved)
7:0 RBR
In non-FIFO mode, this register holds the character received by the UART’s
Receive Shift Register. If fewer than 8 bits are received, the bits are right-
justified and the leading bits are zeroed.
In FIFO mode, this register latches the value of the data byte at the bottom of
the Receive FIFO.
The DLAB bit in the Line Control Register must be set to logic 0 to access this
register.
Register Name: THR
Hex Offset Address: 0xC800 1000 Reset Hex Value: 0x00000000
Register
Description:
Transmit Holding Register
Access: Write Only.
31 87 0
(Reserved) THR
Table 136. Console UART Registers Overview
Address DLAB R/W Name Description