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Intel
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IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
September 2006 DM
Order Number: 252480-006US 131
Intel XScale
®
Processor—Intel
®
IXP42X product line and IXC1100 control plane processors
The download bit acts as a branch flag, signalling to the handler to continue with the
download. This removes the need for a counter in the debug handler.
The overflow flag indicates that the debugger attempted to download the next word
before the debugger read the previous word.
More details on the Download bit, Overflow flag and high-speed download, in general,
can be found in “Transmit/Receive Control Register” on page 98.
Following is example code showing how the Download bit and Overflow flag are used in
the debug handler:
3.6.15.3 Ending a Debug Session
Prior to ending a debug session, the debugger should take the following actions:
1. Clear the DCSR (disable debug, exit Halt Mode, clear all vector traps, disable the
trace buffer)
2. Turn off all breakpoints.
3. Invalidate the mini instruction cache.
4. Invalidate the main instruction cache.
5. Invalidate the BTB.
Table 52. Debug Handler Code: Download Bit and Overflow Flag
hs_write_word_loop:
hs_write_overflow:
bl read_RX @ read data word from host
@@ read TXRXCTRL into the CCs
mrc p14, 0, r15, c14, c0, 0
bcc hs_write_done @ if D bit clear, download complete, exit loop.
beq hs_write_overflow @ if overflow detected, loop until host clears D
bit
str r0, [r6], #4 @ store only if there is no overflow.
b hs_write_word_loop @ get next data word
hs_write_done:
@@ after the loop, if the overflow flag was set, return error message to host
moveq r0, #OVERFLOW_RESPONSE
beq send_response
b write_common_exit