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Intel
®
IXP42X product line and IXC1100 control plane processors—General Purpose Input/
Output (GPIO)
Intel
®
IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
DM September 2006
386 Order Number: 252480-006US
12.0 General Purpose Input/Output (GPIO)
The Intel
®
IXP42X Product Line of Network Processors and IXC1100 Control Plane
Processor provide 16 general-purpose input/output (GPIO) pins for use in capturing
and generating application specific input and output signals. Each GPIO can be
programmed as either an input or an output.
GPIO Pin 14 can be configured similar to GPIO pin 13 or as a clock output. The output-
clock configuration can be set at various speeds, up to 33.33 MHz, with various duty
cycles. GPIO Pin 14 is configured as an input, upon reset.
GPIO Pin 15 can be configured similar to GPIO pin 13 or as a clock output. The output-
clock configuration can be set at various speeds, up to 33.33 MHz, with various duty
cycles. GPIO Pin 15 is configured as a clock output, upon reset. GPIO Pin 15 can be
used to clock the expansion interface, after reset. Each GPIO pin will be capable of
sinking or sourcing 16 mA of current that may be used to drive external LEDs.
When used as an interrupt source, each pin can detect interrupts as active high, active
low, rising edge, falling edge, or transitional. There are eight distinct register functions
used in the GPIO module.
The GPIO is controlled through six registers and two other registers provide GPIO
status. Each register can be read through the APB interface and all registers except
general-purpose input register (GPINR) can be written through the APB interface.
12.1 Using GPIO as Inputs/Outputs
The GPIO on the Intel
®
IXP42X product line and IXC1100 control plane processors can
be configured to be used as general-purpose inputs or general-purpose outputs. Three
16-bit registers are used in order to configure, initialize, and use the general purpose I/
O. These registers are:
• General-Purpose Data Output Register (GPOUTR)
• General-Purpose Output Enable Register (GPOER)
• General-Purpose Input Status Register (GPINR)
The General-Purpose Output Enable Register is used to configure the GPIO pins as an
input or an output. There is a one-for-one relationship between the register bit
mapping and the GPIO. For example, bit 0 of the general-purpose Output Enable
Register corresponds to GPIO 0 and bit 1 of the General-Purpose Output Enable
Register corresponds to GPIO 1.
When a bit of the General-Purpose Enable Register contains logic 0, the corresponding
GPIO will be configured as an output. A logic 1 in the same bit of the General-Purpose
Enable Register will cause the corresponding GPIO to be configured as an input.
For example, the General-Purpose Output Enable Register contains a hexadecimal
value of 0x00000500. GPIO 8 and GPIO 10 will be configured as inputs and all other
GPIO will be configured as outputs. The GPIO that are configured as outputs — by the
values contained in the General-Purpose Enable Register — will be driven by the values
contained in the General-Purpose Data Output Register.