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Intel
®
IXP42X product line and IXC1100 control plane processors—PCI Controller
Intel
®
IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
DM September 2006
220 Order Number: 252480-006US
processors. The IXP42X product line and IXC1100 control plane processors PCI
Controller can be configured to support four 16-Mbyte locations for PCI Target Memory
Cycle transactions using the AHB Memory Base Address (PCI_AHBMEMBASE) register
and the PCI Base Address Registers.
The AHB Memory Base Address (PCI_AHBMEMBASE) register consists of four 8-bit
fields. Each of these fields corresponds to a PCI Base Address Register
• Bits 31:24 of the AHB Memory Base Address (PCI_AHBMEMBASE) register
corresponds to PCI Base Address 0 and the first 16-Mbyte AHB memory location
(AHB base 0)
• Bits 23:16 of the AHB Memory Base Address (PCI_AHBMEMBASE) register
corresponds to PCI Base Address 1 and the second 16-Mbyte AHB memory location
(AHB base 1)
• Bits 15:8 of the AHB Memory Base Address (PCI_AHBMEMBASE) register
corresponds to PCI Base Address 2 and the third 16-Mbyte AHB memory location
(AHB base 2)
• Bits 7:0 of the AHB Memory Base Address (PCI_AHBMEMBASE) register
corresponds to PCI Base Address 3 and the fourth 16-Mbyte AHB memory location
(AHB base 3).
Base Address Register 4 is used to complete accesses to internal PCI Controller
Configuration and Status registers. (These registers are not the PCI Controller PCI
Configuration Registers.) PCI Base Address Register 4 is used to decode that an access
has been made to the Configuration and Status Register Space. There are no AHB
cycles produced for this type of an access, as all accesses to this Base Address Register
will be internal to the PCI controller. Therefore, an address translation register is not
required.
For Base Address Register 5 — which is used to complete PCI bus I/O cycles — the AHB
I/O Base Address (PCI_AHBIOBASE) register is used to translate I/O PCI accesses to
their appropriate AHB locations. The IXP42X product line and IXC1100 control plane
processors PCI Controller can be configured to support a single 256-Byte location for
PCI target I/O cycle transactions, using the AHB I/O Base Address (PCI_AHBIOBASE)
register and PCI Base Address Register 5.
The AHB I/O Base Address (PCI_AHBIOBASE) register consists of a single 24-bit field.
The AHB I/O Base Address (PCI_AHBIOBASE) register is used to determine the upper
24 AHB address bits, when an external initiator on the PCI bus accesses the I/O space
of the IXP42X product line and IXC1100 control plane processors.
6.3.1 Example: AHB Memory Base Address Register, AHB I/O
Base Address Register, and PCI Memory Base Address
Register
The following example can be used to understand the operation of the AHB Memory
Base Address Register (PCI_AHBMEMBASE), AHB I/O Base Address Register
(PCI_AHBIOBASE), and PCI Memory Base Address Register (PCI_PCIMEMBASE).
1. Assume that PCI_AHBMEMBASE = 0x04010506 and PCI_AHBIOBASE =
0x000A1200.
2. Assume that the PCI Bus has gone through configuration and the Base Address
Registers (BAR0 – BAR5) are set as follows:
— BAR0 = 0xA0000000
— BAR1 = 0xA1000000
— BAR2 = 0xA2000000
— BAR3 = 0xA3000000