Filter
Top Products
Intel
®
IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
September 2006 DM
Order Number: 252480-006US 503
Universal Serial Bus (USB) v1.1 Device Controller—Intel
®
IXP42X product line and IXC1100
control plane processors
UDCCS9[RSP] clears when the next OUT packet is received.
18.5.12 UDC Endpoint 10 Control/Status Register (UDCCS10)
The UDC Endpoint 10 Control Status Register contains six bits that are used to operate
endpoint 10, an Interrupt IN endpoint.
18.5.12.1 Transmit FIFO Service (TFS)
The transmit FIFO service bit is set if the FIFO does not contain any data bytes and
UDCCS10[TSP] is not set.
18.5.12.2 Transmit Packet Complete (TPC)
The transmit packet complete bit is be set by the UDC when an entire packet is sent to
the host. When this bit is set, the IR10 bit in the appropriate UDC status/interrupt
register is set if transmit interrupts are enabled.
Register Name: UDCCS9
Hex Offset Address: 0x C800B034 Reset Hex Value: 0x00000000
Register
Description:
Universal Serial Bus Device Controller Endpoint 9Control and Status Register
Access: Read/Write
Bits
31 876543210
(Reserved)
RSP
RNE
(Rsvd)
(Rsvd)
(Rsvd)
ROF
RPC
RFS
X 00000000
Resets (Above)
Register
UDCCS9
Bits Name Description
31:8 Reserved for future use.
7RSP
Receive short packet (read only).
1 = Short packet received and ready for reading.
6RNE
Receive FIFO not empty (read-only).
0 = Receive FIFO empty.
1 = Receive FIFO not empty.
5 (Reserved). Always reads 0.
4 (Reserved). Always reads 0.
3(Reserved)
2ROF
Receive overflow (read/write 1 to clear).
1 = Isochronous data packets are being dropped from the host because the
receiver is full.
1RPC
Receive packet complete (read/write 1 to clear).
0 = Error/status bits invalid.
1 = Receive packet has been received and error/status bits are valid.
0RFS
Receive FIFO service (read-only).
0 = Receive FIFO has less than one data packet.
1 = Receive FIFO has one or more data packets.