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Intel
®
IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
September 2006 DM
Order Number: 252480-006US 509
Universal Serial Bus (USB) v1.1 Device Controller—Intel
®
IXP42X product line and IXC1100
control plane processors
To allow the software to continue to send the STALL condition on the USB bus, the
UDCCS12[FST] bit must be set again. The Intel XScale
®
processor writes a 1 to the
sent stall bit to clear it.
18.5.14.6 Force Stall (FST)
The Intel XScale
®
processor can set the force stall bit to force the UDC to issue a STALL
handshake to all OUT tokens. STALL handshakes continue to be sent until the Intel
XScale
®
processor clears this bit by sending a Clear Feature command.
The UDCCS12[SST] bit is set when the STALL state is actually entered, but this may be
delayed if the UDC is active when the UDCCS12[FST] bit is set. The UDCCS12[FST] bit
is automatically cleared when the UDCCS12[SST] bit is set.
To ensure that no data is transmitted after the Clear Feature command is sent and the
host resumes IN requests, software must clear the transmit FIFO by setting the
UDCCS12[FTF] bit.
18.5.14.7 Receive FIFO Not Empty (RNE)
The receive FIFO not empty bit indicates that unread data remains in the receive FIFO.
This bit must be polled when the UDCCS12[RPC] bit is set to determine if there is any
data in the FIFO that the Intel XScale
®
processor did not read.
The receive FIFO must continue to be read until this bit clears or data will be lost.
18.5.14.8 Receive Short Packet (RSP)
The UDC uses the receive short packet bit to indicate that the received OUT packet in
the active buffer currently being read is a short packet or zero-sized packet. This bit is
updated by the UDC after the last byte is read from the active buffer and reflects the
status of the new active buffer.
If UDCCS12[RSP] is a 1 and UDCCS12[RNE] is a 0, it indicates a zero-length packet. If
a zero-length packet is present, the Intel XScale
®
processor must not read the data
register. UDCCS12[RSP] is cleared when the next OUT packet is received.
Register Name: UDCCS12
Hex Offset Address: 0 x C800 B040 Reset Hex Value: 0 x 00000000
Register
Description:
Universal Serial Bus Device Controller Endpoint 12 Control and Status Register
Access: Read/Write
Bits
31 876543210
(Reserved)
RSP
RNE
FST
SST
(Rsvd)
(Rsvd)
RPC
RFS
X 00000000
Resets (Above)