Intel IXP42X Personal Computer User Manual


 
Intel
®
IXP42X product line and IXC1100 control plane processors—Intel XScale
®
Processor
Intel
®
IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
DM September 2006
58 Order Number: 252480-006US
The Intel XScale processor provides a global unlock command for the instruction cache.
Writing to coprocessor 15, register 9 unlocks all the locked lines in the instruction
cache and leaves them valid. These lines then become available for the round-robin
replacement algorithm. (See Table 20, “Cache Lock-Down Functions” on page 83 for
the exact command.)
3.3 Branch Target Buffer
The Intel XScale processor uses dynamic branch prediction to reduce the penalties
associated with changing the flow of program execution. The Intel XScale processor
features a branch target buffer that provides the instruction cache with the target
address of branch type instructions. The branch target buffer is implemented as a 128-
entry, direct-mapped cache.
This section is primarily for those optimizing their code for performance. An
understanding of the branch target buffer is needed in this case so that code can be
scheduled to best utilize the performance benefits of the branch target buffer.
3.3.1 Branch Target Buffer (BTB) Operation
The BTB stores the history of branches that have executed along with their targets.
Figure 10 shows an entry in the BTB, where the tag is the instruction address of a
previously executed branch and the data contains the target address of the previously
executed branch along with two bits of history information.
Example 7. Locking Code into the Cache
lockMe: ; This is the code that will be locked into the cache
mov r0, #5
add r5, r1, r2
. . .
lockMeEnd:
. . .
codeLock: ; here is the code to lock the “lockMe” routine
ldr r0, =(lockMe AND NOT 31); r0 gets a pointer to the first line we
should lock
ldr r1, =(lockMeEnd AND NOT 31); r1 contains a pointer to the last line we
should lock
lockLoop:
mcr p15, 0, r0, c9, c1, 0; lock next line of code into ICache
cmp r0, r1 ; are we done yet?
add r0, r0, #32 ; advance pointer to next line
bne lockLoop ; if not done, do the next line