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Intel
®
IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
September 2006 DM
Order Number: 252480-006US 13
—Intel
®
IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
18.5.2.5 Sent Stall (SST)...................................................................... 484
18.5.2.6 Force Stall (FST)..................................................................... 484
18.5.2.7 Receive FIFO Not Empty (RNE) ................................................. 484
18.5.2.8 Setup Active (SA) ................................................................... 484
18.5.3 UDC Endpoint 1 Control/Status Register (UDCCS1) ................................... 485
18.5.3.1 Transmit FIFO Service (TFS)..................................................... 485
18.5.3.2 Transmit Packet Complete (TPC)............................................... 486
18.5.3.3 Flush Tx FIFO (FTF)................................................................. 486
18.5.3.4 Transmit Underrun (TUR)......................................................... 486
18.5.3.5 Sent STALL (SST) ................................................................... 486
18.5.3.6 Force STALL (FST) .................................................................. 486
18.5.3.7 Bit 6 Reserved........................................................................ 487
18.5.3.8 Transmit Short Packet (TSP) .................................................... 487
18.5.4 UDC Endpoint 2 Control/Status Register (UDCCS2) ................................... 487
18.5.4.1 Receive FIFO Service (RFS)...................................................... 488
18.5.4.2 Receive Packet Complete (RPC) ................................................ 488
18.5.4.3 Bit 2 Reserved........................................................................ 488
18.5.4.4 Bit 2 Reserved........................................................................ 488
18.5.4.5 Sent Stall (SST)...................................................................... 488
18.5.4.6 Force Stall (FST)..................................................................... 488
18.5.4.7 Receive FIFO Not Empty (RNE) ................................................. 488
18.5.4.8 Receive Short Packet (RSP)...................................................... 489
18.5.5 UDC Endpoint 3 Control/Status Register (UDCCS3) ................................... 490
18.5.5.1 Transmit FIFO Service (TFS)..................................................... 490
18.5.5.2 Transmit Packet Complete (TPC)............................................... 490
18.5.5.3 Flush Tx FIFO (FTF)................................................................. 490
18.5.5.4 Transmit Underrun (TUR)......................................................... 490
18.5.5.5 Bit 4 Reserved........................................................................ 490
18.5.5.6 Bit 5 Reserved........................................................................ 490
18.5.5.7 Bit 6 Reserved........................................................................ 490
18.5.5.8 Transmit Short Packet (TSP) .................................................... 491
18.5.6 UDC Endpoint 4 Control/Status Register (UDCCS4) ................................... 491
18.5.6.1 Receive FIFO Service (RFS)...................................................... 491
18.5.6.2 Receive Packet Complete (RPC) ................................................ 492
18.5.6.3 Receive Overflow (ROF)........................................................... 492
18.5.6.4 Bit 3 Reserved........................................................................ 492
18.5.6.5 Bit 4 Reserved........................................................................ 492
18.5.6.6 Bit 5 Reserved........................................................................ 492
18.5.6.7 Receive FIFO Not Empty (RNE) ................................................. 492
18.5.6.8 Receive Short Packet (RSP)...................................................... 492
18.5.7 UDC Endpoint 5 Control/Status Register (UDCCS5) ................................... 493
18.5.7.1 Transmit FIFO Service (TFS)..................................................... 493
18.5.7.2 Transmit Packet Complete (TPC)............................................... 493
18.5.7.3 Flush Tx FIFO (FTF)................................................................. 494
18.5.7.4 Transmit Underrun (TUR)......................................................... 494
18.5.7.5 Sent STALL (SST) ................................................................... 494
18.5.7.6 Force STALL (FST) .................................................................. 494
18.5.7.7 Bit 6 Reserved........................................................................ 494
18.5.7.8 Transmit Short Packet (TSP) .................................................... 495
18.5.8 UDC Endpoint 6 Control/Status Register .................................................. 495
18.5.8.1 Transmit FIFO Service (TFS)..................................................... 496
18.5.8.2 Transmit Packet Complete (TPC)............................................... 496
18.5.8.3 Flush Tx FIFO (FTF)................................................................. 496
18.5.8.4 Transmit Underrun (TUR)......................................................... 496
18.5.8.5 Sent STALL (SST) ................................................................... 496
18.5.8.6 Force STALL (FST) .................................................................. 496
18.5.8.7 Bit 6 Reserved........................................................................ 497
18.5.8.8 Transmit Short Packet (TSP) .................................................... 497
18.5.9 UDC Endpoint 7 Control/Status Register (UDCCS7) ................................... 498