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Intel
®
IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
September 2006 DM
Order Number: 252480-006US 565
AHB Queue Manager (AQM)—Intel
®
IXP42X product line and IXC1100 control plane processors
21.5.6 Interrupt 0 Status Flag Source Select Register 0 – 3
The interrupt source for each queue is selectable as the positive or negative (NOT)
edge-sensitive version of any one of the E, NE, NF or F status flag bits on interrupt 0,
aqm_int[0]. The selection is configurable for interrupt 0 only, while interrupt 1,
aqm_int[1], is hard wired to the NE Status Flag bit.
Register Name: QUEUPPSTATF
Physical Address:
0x041C
Reset Hex Value: 0x00000000
Register Description: Queue status register for queues 32-63. F: ‘1’ – flag set
Access: Read/Write
3
1
2
4
2
3
1
6
1
5
87 0
Q63 F
Q62 F
Q61 F
Q60 F
Q59 F
Q58 F
Q57 F
Q56 F
Q55 F
Q54 F
Q53 F
Q52 F
Q51 F
Q50 F
Q49 F
Q48 F
Q47 F
Q46 F
Q45 F
Q44 F
Q43 F
Q42 F
Q41 F
Q40 F
Q39 F
Q38 F
Q37 F
Q36 F
Q35 F
Q34 F
Q33 F
Q32 F
Register Name: INT0SRCSELREG (0 <= n <=3)
Physical Address:
Reg #n 0x(0420 + 4n)
Reset Hex Value: 0x00000000
Register Description: Status Flag selection for interrupt 0 source on queues 0-31.
Access: Read/Write
3
1
2
4
2
3
1
6
1
5
87 0
Reserved
Queue (8n + 7) Stat Src Sel
Reserved
Queue (8n + 6) Stat Src Sel
Reserved
Queue (8n + 5) Stat Src Sel
Reserved
Queue (8n + 4) Stat Src Sel
Reserved
Queue (8n + 3) Stat Src Sel
Reserved
Queue (8n + 2) Stat Src Sel
Reserved
Queue (8n + 1) Stat Src Sel
Spec for 0
Queue (8n) Stat Src Sel