Filter
Top Products
Intel
®
IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
September 2006 DM
Order Number: 252480-006US 49
Intel XScale
®
Processor—Intel
®
IXP42X product line and IXC1100 control plane processors
3.1.3.3 Locking Entries
Individual entries can be locked into the instruction and data TLBs. See Table 20,
“Cache Lock-Down Functions” on page 83 for the exact commands. If a lock operation
finds the virtual address translation already resident in the TLB, the results are
unpredictable. An invalidate by entry command before the lock command will ensure
proper operation. Software can also accomplish this by invalidating all entries, as
shown in Example 2 on page 50.
Locking entries into either the instruction TLB or data TLB reduces the available number
of entries (by the number that was locked down) for hardware to cache other virtual to
physical address translations.
A procedure for locking entries into the instruction TLB is shown in Example 2 on
page 50.
If a MMU abort is generated during an instruction or data TLB lock operation, the Fault
Status Register is updated to indicate a Lock Abort (see “Data Aborts” on page 156),
and the exception is reported as a data abort.
Example 1. Enabling the MMU
; This routine provides software with a predictable way of enabling the MMU.
; After the CPWAIT, the MMU is guaranteed to be enabled. Be aware
; that the MMU will be enabled sometime after MCR and before the instruction
; that executes after the CPWAIT.
; Programming Note: This code sequence requires a one-to-one virtual to
; physical address mapping on this code since
; the MMU may be enabled part way through. This would allow the instructions
; after MCR to execute properly regardless the state of the MMU.
MRC P15,0,R0,C1,C0,0; Read CP15, register 1
ORR R0, R0, #0x1; Turn on the MMU
MCR P15,0,R0,C1,C0,0; Write to CP15, register 1
; For a description of CPWAIT, see
; “Additions to CP15 Functionality” on page 153
CPWAIT
; The MMU is guaranteed to be enabled at this point; the next instruction or
; data address will be translated.