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Intel
®
IXP42X product line and IXC1100 control plane processors—PCI Controller
Intel
®
IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
DM September 2006
246 Order Number: 252480-006US
As described previously, during DMA transfers the DS bit in the DMA length registers
controls byte-lane routing. Figure 51 shows the byte lane routing between the PCI bus
and the South AHB during DMA transfers. The DMA channels are word-only accesses.
Figure 50. Byte Lane Routing During AHB Memory Mapped Accesses of the PCI Bus –
AHB configured as a Little-Endian Bus
31
24
Write,
pci_csr.ADS = 1
AHB Data
3
2
1
0
23
16
15
8
7
0
31
24
11 10
01
00
23
16
15
8
7
0
31
24
3 2
1
0
23
16
15
8
7
0
31
24
11 10
01
00
23
16
15
8
7
0
AHB Data
PCI Data PCI Data
Read,
pci_csr.ADS = 1
31
24
Write,
pci_csr.ADS = 0
AHB Data
3
2
1
0
23
16
15
8
7
0
31
24
11 10
01
00
23
16
15
8
7
0
31
24
3 2
1
0
23
16
15
8
7
0
31
24
11 10
01
00
23
16
15
8
7
0
AHB Data
PCI Data PCI Data
Read,
pci_csr.ADS = 0