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Intel
®
IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
September 2006 DM
Order Number: 252480-006US 57
Intel XScale
®
Processor—Intel
®
IXP42X product line and IXC1100 control plane processors
As a result: no fetches of cacheable code should occur while locking instructions
into the cache.
• The code being locked into the cache must be cacheable
• The instruction cache must be enabled and invalidated prior to locking down lines.
Failure to follow these requirements will produce unpredictable results when accessing
the instruction cache.
System programmers should ensure that the code to lock instructions into the cache
does not reside closer than 128 bytes to a non-cacheable/cacheable page boundary. If
the processor fetches ahead into a cacheable page, then the first requirement noted
above could be violated.
Lines are locked into a set starting at way 0 and may progress up to way 27; which set
a line gets locked into depends on the set index of the virtual address. Figure 9 is an
example (32-Kbyte cache) of where lines of code may be locked into the cache along
with how the round-robin pointer is affected.
Software can lock down several different routines located at different memory
locations. This may cause some sets to have more locked lines than others as shown in
Figure 9.
Example 7 on page 58 shows how a routine, called “lockMe” in this example, might be
locked into the instruction cache. Note that it is possible to receive an exception while
locking code (see “Event Architecture” on page 154).
Figure 9. Locked Line Effect on Round-Robin Replacement
way 0
way 1
way 7
way 8
way 22
way 23
way 30
way 31
set 1
set 31
Locked
set 0
Locked
set 2
Locked
...
set 0: 8 ways locked, 24 ways available for round robin replacement
set 1: 23 ways locked, 9 ways available for round robin replacement
set 2: 28 ways locked, only way 28-31 available for replacement
set 31: all 32 ways available for round robin replacement
...
......
32
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