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Intel
®
IXP42X product line and IXC1100 control plane processors—Universal Asynchronous
Receiver Transceiver (UART)
Intel
®
IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
DM September 2006
342 Order Number: 252480-006US
Receive Interface. Lines Status Register bits 1 through 4 specify which error(s) has
occurred — for the character at the bottom of the FIFO or in the Receive Buffer
Register.
In FIFO mode, Line Status Register bit 1 through 3 is stored with each received
character in the Receive FIFO. The Line Status Register shows the status bits of the
character at the bottom of the Receive FIFO. When the character at the bottom of the
FIFO has errors, the Line Status error bits are set and are not cleared until the Intel
XScale processor reads the Line Status Register. Even if the character in the FIFO is
read — and a new character is now at the bottom of the FIFO — the interrupts will not
be cleared until the Line-Status Register is read.
Character-error status is handled in the same way as when the UART is operating in
interrupt mode of operation. Setting Line-Status Register bit 5 to logic 1 indicates that
the Transmit FIFO or the Transmit Holding Register is requesting data. Line Status
Register bit 6 identifies that both the Transmit FIFO and the Transmit Shift Register
have no data. Line Status Register bit 7 indicates the status of any errors in the Receive
FIFO.
In non-FIFO mode, three of the LSR register bits — parity error, framing error, and
break interrupt — show the error status of the character that has just been received.
The Receive Time-Out Interrupt is separated from the Receive-Data-Available Interrupt
to prevent an Interrupt Controller routine and a Data Service controller routing from
servicing the receive FIFO at the same time. Bit 7 of the Interrupt-Enable Register is
used as the enable bit of Data Service requests. Bit 5 of the Interrupt Enable Register is
used as the enable bit of NRZ-coding enable.
Bits 7 and 5 are not implemented by the IXP42X product line and IXC1100 control
plane processors. The use of bit 7 through bit 4, of the Interrupt-Enable Register, is
defined differently from the register definition of standard 16550 UART.
The Interrupt-Enable Register is initialized to all zeros after receiving a reset. The
Interrupt Identification Register is a hexadecimal 0x01. Bit 5 and Bit 4 of the Interrupt
Identification Register will always be logic 0.
10.3 Transmitting and Receiving UART Data
Transmitting and receiving data — using the IXP42X product line and IXC1100 control
plane processors’ UARTs — is achievable in two modes: Non-FIFO Mode and FIFO Mode.
In Non-FIFO mode, data will be transmitted and received using two registers — the
Transmit-Holding Register (THR) and the Receive-Buffer Register (RBR) — along with
the UART control, status, and interrupt registers.
In FIFO mode, data will be transmitted and received using two 64-entry FIFOs, the
Transmit FIFO, and the Receive FIFO — along with the UART Control, Status, and
Interrupt registers.
The Transmit FIFO is 64 entries deep by 8 bits wide. The Transmit FIFO sizing allows a
complete 8-bit data character to be stored in each entry. When characters smaller than
8 bits are transmitted, they are right-justified.
If a 5-bit character is to be transmitted, the character is represented by a binary
10110. The value located in the FIFO entry will be hexadecimal 0x16.
The Receive FIFO is 64 entries deep and 11 bits wide. The Receive FIFO sizing allows
for an 8-bit character to be received along with the over-run flag, parity error flag, and
framing error flag for each received character. Smaller characters will be right-justified,
as described for the transmit FIFO.