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Intel
®
IXP42X product line and IXC1100 control plane processors—Universal Serial Bus (USB)
v1.1 Device Controller
Intel
®
IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
DM September 2006
508 Order Number: 252480-006US
18.5.14 UDC Endpoint 12 Control/Status Register (UDCCS12)
The UDC Endpoint 12 Control/Status Register contains seven bits that are used to
operate endpoint 12, a Bulk OUT endpoint.
18.5.14.1 Receive FIFO Service (RFS)
The receive FIFO service bit is set if the receive FIFO has one complete data packet in it
and the packet has been error checked by the UDC. A complete packet may be
64 bytes, a short packet, or a zero packet.
This bit is not cleared until all data has been read from both buffers.
18.5.14.2 Receive Packet Complete (RPC)
The receive packet complete bit is set by the UDC when an OUT packet is received.
When this bit is set, the IR12 bit in the appropriate UDC status/interrupt register is set,
if receive interrupts are enabled.
This bit can be used to validate the other status/error bits in the endpoint 12 control/
status register. The UDCCS12[RPC] bit is cleared by writing a 1 to it. The UDC issues
NAK handshakes to all OUT tokens while this bit is set and both buffers have unread
data.
18.5.14.3 Bit 2 Reserved
Bit 2 is reserved for future use.
18.5.14.4 Bit 3 Reserved
Bit 3 is reserved for future use.
18.5.14.5 Sent Stall (SST)
The sent stall bit is set by the UDC in response to FST successfully forcing a user-
induced STALL on the USB bus. This bit is not set if the UDC detects a protocol violation
from the host PC when a STALL handshake is returned automatically. In either event,
the Intel XScale
®
processor does not intervene and the UDC clears the STALL status
when the host sends a CLEAR_FEATURE command.
Any valid data in the FIFO remains valid and the software must unload it. The endpoint
operation continues normally and does not send another STALL condition, even if the
UDCCS12[SST] bit is set.
2FTF
Flush Tx FIFO (always read 0/ write a 1 to set).
1 = Flush Contents of TX FIFO.
1TPC
Transmit packet complete (read/write 1 to clear).
0 = Error/status bits invalid.
1 = Transmit packet has been sent and error/status bits are valid.
0TFS
Transmit FIFO service (read-only).
0 = Transmit FIFO has no room for new data.
1 = Transmit FIFO has room for at least 1 complete data packet.
Register
UDCCS11 (Sheet 2 of 2)
Bits Name Description