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Intel
®
IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
September 2006 DM
Order Number: 252480-006US 93
Intel XScale
®
Processor—Intel
®
IXP42X product line and IXC1100 control plane processors
• Exception vector trap
• Trace-buffer full break
When a debug exception occurs, the processor’s actions depend on whether the debug
unit is configured for Halt mode or Monitor mode.
Table 34 shows the priority of debug exceptions relative to other processor exceptions.
3.6.5.1 Halt Mode
The debugger turns on Halt mode through the JTAG interface by scanning in a value
that sets the bit in DCSR. The debugger turns off Halt mode through JTAG, either by
scanning in a new DCSR value or by a TRST. Processor reset does not effect the value
of the Halt mode bit.
When halt mode is active, the processor uses the reset vector as the debug vector. The
debug handler and exception vectors can be downloaded directly into the instruction
cache, to intercept the default vectors and reset handler, or they can be resident in
external memory. Downloading into the instruction cache allows a system with memory
problems, or no external memory, to be debugged. Refer top “Downloading Code in
ICache” on page 116 for details about downloading code into the instruction cache.
During Halt mode, software running on IXP42X product line and IXC1100 control plane
processors cannot access DCSR, or any of hardware breakpoint registers, unless the
processor is in Special Debug State (SDS), described below.
When a debug exception occurs during Halt mode, the processor takes the following
actions:
• Disables the trace buffer
• Sets DCSR.moe encoding
• Processor enters a Special Debug State (SDS)
• For data breakpoints, trace buffer full break, and external debug break:
R14_dbg = PC of the next instruction to execute + 4
for instruction breakpoints and software breakpoints and vector traps:
R14_dbg = PC of the aborted instruction + 4
• SPSR_dbg = CPSR
• CPSR[4:0] = 0b10101 (DEBUG mode)
Table 34. Event Priority
Event Priority
Reset 1
Vector Trap 2
data abort (precise) 3
data bkpt 4
data abort (imprecise) 5
external debug break, trace-buffer full 6
FIQ 7
IRQ 8
instruction breakpoint 9
pre-fetch abort 10
undef, SWI, software Bkpt 11