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Intel
®
IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
September 2006 DM
Order Number: 252480-006US 401
Interrupt Controller—Intel
®
IXP42X product line and IXC1100 control plane processors
The FIQ Status Register and the IRQ Status Register are 32-bit registers that have a
one-for-one relationship with the interrupt number. Interrupt number 0 (WAN/Voice
NPE) will be the status represented on bit 0 of both the FIQ Status Register and the IRQ
Status Registers. Interrupt number 31 will be the status represented on bit 31 of both
the FIQ Status Register and the IRQ Status Registers.
Reading logic 1 from a bit in either the FIQ Status Register or the IRQ Status Registers
represent that the device connected to that particular interrupt number has asserted an
interrupt to the Interrupt Controller. For example, a read is performed on the FIQ
Status Register and the result returned is a hexadecimal 0x00000001. The Interrupt
Status Register is telling the Intel XScale processor that the interrupt number 0 (WAN/
Voice NPE) has caused an interrupt and the interrupt is assigned as an FIQ interrupt.
The Intel XScale processor will service the interrupt and clear the interrupt by updating
the register that caused the interrupt condition in the WAN/Voice NPE. The same action
will be applied to an interrupt that would be caused by an IRQ interrupt. Allowing the
capability to separate the FIQ and IRQ interrupts allows separate interrupt service
routines to be built based on the type of interrupt received. This allows greater control
in application that may be developed by the IXP42X product line and IXC1100 control
plane processors.
The FIQ Status Register and IRQ Status Register are set to all zeros upon reset.
The IXP42X product line and IXC1100 control plane processors also allows the
capability to read the highest-priority IRQ interrupt or the highest-priority FIQ interrupt
as determined by the priority algorithm described in “Interrupt Priority” on page 398.
The highest-priority IRQ interrupt can be read by reading the IRQ Highest-Priority
Register (INTR_IRQ_ENC_ST). The highest-priority FIQ interrupt can be read by
reading the FIQ Highest-Priority Register (INTR_FIQ_ENC_ST). The IRQ Highest-
Priority Register and the FIQ Highest-Priority Registers are 6-bit registers that will
return the highest-priority interrupt of each the IRQ interrupts and the FIQ interrupts.
The value obtained by reading the IRQ Highest-Priority Register will be the interrupt
number of the highest-priority IRQ interrupt, incremented by one and the sum of the
add left shifted by two bits. Therefore, the six bits — that contain the IRQ highest
priority — are actually located in bits 2 through 7 of the IRQ Highest-Priority Register.
For example, interrupt number 1 (Ethernet NPE A) is the highest-priority IRQ interrupt,
the value obtained when reading the IRQ Highest-Priority Interrupt Register would be
hexadecimal 0x00000008. A value of 0 — returned when reading the IRQ Highest-
Priority Register — signifies that no IRQ interrupts are pending.
The IRQ Highest-Priority Register will be reset to a value of 0. The FIQ Highest-Priority
Register will behave in an identical fashion to the IRQ Highest-Priority Register.
13.5 Interrupt Controller Register Description
Table 149. Interrupt Controller Registers
Address R/W Name Description
0xC8003000 R INTR_ST Interrupt Status Register
0xC8003004 R/W INTR_EN Interrupt Enable Register
0xC8003008 R/W INTR_SEL Interrupt Select Register
0xC800300C R INTR_IRQ_ST IRQ Status register
0xC8003010 R INTR_FIQ_ST FIQ status Register