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Intel
®
IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor—
Intel
®
IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
DM September 2006
12 Order Number: 252480-006US
15.2.45Unicast Address 6 .................................................................................444
15.2.46Core Control ........................................................................................444
16.0 Ethernet MAC B ......................................................................................................446
17.0 High-Speed Serial Interfaces .................................................................................448
17.1 High-Speed Serial Interface Receive Operation ....................................................448
17.2 High-Speed Serial Interface Transmit Operation...................................................449
17.3 Configuration of the High-Speed Serial Interface..................................................450
17.4 Obtaining High-Speed, Serial Synchronization......................................................453
17.5 HSS Registers and Clock Configuration ...............................................................454
17.5.1 HSS Clock and Jitter..............................................................................455
17.5.2 Overview of HSS Clock Configuration.......................................................455
17.6 HSS Supported Framing Protocols......................................................................457
17.6.1 T1 ......................................................................................................457
17.6.2 E1 ......................................................................................................459
17.6.3 MVIP...................................................................................................460
17.6.3.1 MVIP using 2.048Mbps Backplane..............................................461
17.6.3.2 MVIP Using 4.096-Mbps Backplane ............................................463
17.6.3.3 MVIP Using 8.192-Mbps Backplane ............................................464
18.0 Universal Serial Bus (USB) v1.1 Device Controller..................................................468
18.1 USB Overview .................................................................................................468
18.2 Device Configuration ........................................................................................469
18.3 USB Operation ................................................................................................470
18.3.1 Signalling Levels...................................................................................470
18.3.2 Bit Encoding.........................................................................................471
18.3.3 Field Formats .......................................................................................472
18.3.4 Packet Formats ....................................................................................473
18.3.4.1 Token Packet Type ..................................................................474
18.3.4.2 Start-of-Frame Packet Type......................................................474
18.3.4.3 Data Packet Type ....................................................................474
18.3.4.4 Handshake Packet Type ...........................................................475
18.3.5 Transaction Formats..............................................................................475
18.3.5.1 Bulk Transaction Type..............................................................475
18.3.5.2 Isochronous Transaction Type...................................................476
18.3.5.3 Control Transaction Type..........................................................476
18.3.5.4 Interrupt Transaction Type .......................................................477
18.3.6 UDC Device Requests ............................................................................477
18.3.7 UDC Configuration ................................................................................478
18.4 UDC Hardware Connections...............................................................................479
18.4.1 Self-Powered Device .............................................................................479
18.4.2 Bus-Powered Devices ............................................................................479
18.5 Register Descriptions........................................................................................479
18.5.1 UDC Control Register (UDCCR) ...............................................................481
18.5.1.1 UDC Enable ............................................................................481
18.5.1.2 UDC Active.............................................................................481
18.5.1.3 UDC Resume (RSM).................................................................481
18.5.1.4 Resume Interrupt Request (RESIR)............................................481
18.5.1.5 Suspend Interrupt Request (SUSIR)...........................................482
18.5.1.6 Suspend/Resume Interrupt Mask (SRM) .....................................482
18.5.1.7 Reset Interrupt Request (RSTIR) ...............................................482
18.5.1.8 Reset Interrupt Mask (REM)......................................................482
18.5.2 UDC Endpoint 0 Control/Status Register (UDCCS0) ...................................483
18.5.2.1 OUT Packet Ready (OPR)..........................................................483
18.5.2.2 IN Packet Ready (IPR) .............................................................483
18.5.2.3 Flush Tx FIFO (FTF) .................................................................484
18.5.2.4 Device Remote Wake-Up Feature (DRWF)...................................484