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Intel
®
IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
September 2006 DM
Order Number: 252480-006US 345
Universal Asynchronous Receiver Transceiver (UART)—Intel
®
IXP42X product line and IXC1100
control plane processors
10.4.2 Transmit Holding Register
10.4.3 Divisor Latch Low Register
Register RBR
Bits Name Description
31:8 (Reserved)
7:0 RBR
In non-FIFO mode, this register holds the character received by the UART’s
Receive Shift Register. If fewer than 8 bits are received, the bits are right-
justified and the leading bits are zeroed.
In FIFO mode, this register latches the value of the data byte at the bottom of
the Receive FIFO.
The DLAB bit in the Line Control Register must be set to logic 0 to access this
register.
Register Name: THR
Hex Offset Address: 0xC800 0000 Reset Hex Value: 0x00000000
Register
Description:
Transmit Holding Register
Access: Write Only.
31 87 0
(Reserved) THR
Register
THR
Bits Name Description
31:8 (Reserved)
7:0 THR
In Non-FIFO mode, this register holds the next data byte to be transmitted.
When the Transmit Shift Register becomes empty, the contents of the Transmit
Holding Register are loaded into the shift register and the transmit data request
(TDRQ) bit in the Line Status Register is set to 1.
In FIFO mode, writing to THR puts data to the top of the Transmit FIFO. The
data at the bottom of the Transmit FIFO is loaded to the shift register when the
shift register becomes empty.
The DLAB bit in the Line Control Register must be set to logic 0 to access this
register.
Register Name: DLL
Hex Offset Address: 0xC800 0000 Reset Hex Value: 0x00000002
Register
Description:
Divisor Latch Low Register
Access: Read/Write.
31 87 0
(Reserved) DLL