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Intel
®
IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
September 2006 DM
Order Number: 252480-006US 325
Expansion Bus Controller—Intel
®
IXP42X product line and IXC1100 control plane processors
Only two bits in Configuration Register 1 are currently defined. Under software control,
they allow interrupts to be generated to the Interrupt Controller.
Register Name: EXP_CNFG1
Hex Offset Address: 0XC4000024 Reset Hex Value: 0x00000000
Register
Description:
Configuration Register #1
Access: Read/Write.
31 987 210
(Reserved)
BYTE_SWAP_EN
(Reserved)
SW_ INT1
SW_ INT0
Table 126. Expansion Bus Configuration Register 1-Bit Definition
Bit Name Description
31:16 (Reserved)
8 BYTE_SWAP_EN
Sets byte swapping at the Intel XScale processor
1 = byte swapping enabled
0 = byte swapping disabled
Note: See note, below.
7:2 (Reserved)
1SW_INT1
1 = Generate interrupt
0 = Disable interrupt
0SW_INT0
1 = Generate interrupt
0 = Disable interrupt
Note: The selection between address or data coherency is controlled by a software-programmable,
P-attribute bit in the Memory Management Unit (MMU) and the BYTE_SWAP_EN bit of the IXP42X
product line and IXC1100 control plane processors. The BYTE_SWAP_EN bit will be from Expansion
Bus Controller Configuration Register 1, Bit 8. When the IXP42X product line and IXC1100 control
plane processors is reset, this bit will reset to 0.
The default endian conversion method for IXP42X product line and IXC1100 control plane processors
is address coherency. This was selected to enable backward compatible with the Intel
®
IXP425
Network Processor A-Step processor.
The BYTE_SWAP_EN bit is an enable bit that enables data coherency to be performed, based on the
P-attribute bit.
When the bit is 0, address coherency is always performed.
When the bit is 1, the type of coherency depends on the P-attribute bit.
The P-attribute bit is associated with each 1-Mbyte page. The P-attribute bit is output, from the Intel
XScale processor, with any store or load access associated with that page.