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Intel
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IXP42X product line and IXC1100 control plane processors—PCI Controller
Intel
®
IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
DM September 2006
240 Order Number: 252480-006US
The PCI Door Bell Register (PCI_PCIDOORBELL) register can only be written by the
AHB. The external PCI device must write logic 1 to all set bits in the PCI Door Bell
Register (PCI_PCIDOORBELL) in order to clear the bits set by the Intel XScale
processor.
An example of using the PCI Door Bell (PCI_PCIDOORBELL) is as follows:
1. The Intel XScale processor writes logic 1 to a bit or pattern of bits in the PCI Door
Bell Register (PCI_PCIDOORBELL) to generate an interrupt on the PCI bus using
PCI_INTA_N.
2. An external PCI device reads the PCI Door Bell Register (PCI_PCIDOORBELL) and
writes logic 1(s) to all set bits to clear the set bit(s). This causes the interrupt that
is asserted to de-assert.
6.10 PCI Controller Interrupts
The PCI Controller supports generation of a single PCI interrupt and interrupts to the
Intel XScale processor. Complete control of the interrupt sources and enabling is
provided using two registers: the PCI Interrupt Status Register (PCI_ISR) and PCI
Interrupt Enable Register (PCI_INTEN).
6.10.1 PCI Interrupt Generation
The PCI Door Bell Register (PCI_PCIDOORBELL) is used to generate an interrupt on the
PCI Bus using the PCI_INTA_N signal. For more information on the interrupt
generation, see “PCI Controller Door Bell Register” on page 239.
The PDB bit — Bit 7 of the PCI Interrupt Enable Register (PCI_INTEN) — is used to
enable the external PCI Interrupt. When bit 7 is set to logic 1, the external PCI
Interrupt logic is enabled. When bit 7 is set to logic 0 the external PCI Interrupt logic is
disabled.
Bit 7 of the PCI Interrupt Status Register (PCI_ISR) displays the status of the external
PCI Interrupt. This bit will be set to logic 1 when any of the PCI_PCIDOORBELL bits are
set to logic 1.
6.10.2 Internal Interrupt Generation
The PCI Controller employs three signals internal to the IXP42X product line and
IXC1100 control plane processors that are sent to the Interrupt Controller to signal the
Intel XScale processor at the occurrence of various events:
• PCI Controller Interrupt signal (PCC_INT) — A general-purpose interrupt
• PCI Controller AHB to PCI DMA Interrupt signal (PCC_ATPDMA_INT) — A DMA
interrupt
• PCI Controller PCI to AHB DMA Interrupt signal (PCC_PTADMA_INT) — A DMA
interrupts.
All interrupts are active high and remain asserted until the Intel XScale processor
clears the interrupting source by writing the appropriate Configuration and Status
Register bits in the PCI Controller.
The PCI Controller Interrupt signal (PCC_INT) can be asserted when:
• A PCI error occurs
• An AHB error occurs
• A AHB-to-PCI DMA transfer is complete or terminates due to an error
• A PCI-to-AHB DMA transfer is complete or terminates due to an error