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Intel
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IXP42X product line and IXC1100 control plane processors—Intel XScale
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Processor
Intel
®
IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
DM September 2006
146 Order Number: 252480-006US
3.8.3 Extensions to ARM
*
Architecture
The Intel XScale processor adds a few extensions to the ARM Version 5TE architecture
to meet the needs of various markets and design requirements. The following is a list of
the extensions which are discussed in the next sections.
• A DSP coprocessor (CP0) has been added that contains a 40-bit accumulator and
eight new instructions.
• New page attributes were added to the page table descriptors. The C and B page
attribute encoding was extended by one more bit to allow for more encodings:
write allocate and mini-data cache.
• Additional functionality has been added to coprocessor 15. Coprocessor 14 was also
created.
• Enhancements were made to the Event Architecture, which include instruction
cache and data cache parity error exceptions, breakpoint events, and imprecise
external data aborts.
3.8.3.1 DSP Coprocessor 0 (CP0)
The Intel XScale processor adds a DSP coprocessor to the architecture for the purpose
of increasing the performance and the precision of audio processing algorithms. This
coprocessor contains a 40-bit accumulator and eight new instructions.
The 40-bit accumulator is referenced by several new instructions that were added to
the architecture; MIA, MIAPH and MIAxy are multiply/accumulate instructions that
reference the 40-bit accumulator instead of a register specified accumulator. MAR and
MRA provide the ability to read and write the 40-bit accumulator.
Access to CP0 is always allowed in all processor modes when bit 0 of the Coprocessor
Access Register is set. Any access to CP0 when this bit is clear will cause an undefined
exception. (See “Register 15: Coprocessor Access Register” on page 85 for more
details). Note that only privileged software can set this bit in the Coprocessor Access
Register located in CP15.
The 40-bit accumulator will need to be saved on a context switch if multiple processes
are using it.
Two new instruction formats were added for coprocessor 0: Multiply with Internal
Accumulate Format and Internal Accumulate Access Format. The formats and
instructions are described next.
3.8.3.1.1 Multiply With Internal Accumulate Format
A new multiply format has been created to define operations on 40-bit accumulators.
Table 7, “MRC/MCR Format” on page 74 shows the layout of the new format. The op
code for this format lies within the coprocessor register transfer instruction type. These
instructions have their own syntax.