Filter
Top Products
Intel
®
IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
September 2006 DM
Order Number: 252480-006US 543
UTOPIA Level-2—Intel
®
IXP42X product line and IXC1100 control plane processors
In addition to supporting data transmission and HEC generation, the Transmit Module
maintains some statistical values. The statistics that can be maintained are on a single
physical port address on a specified VPI/VCI address value. The 32-bit counters will
maintain the following counts:
• The number of cells transmitted
• The number of idle cells transmitted
The counters are not cleared when read by the Network Processor Engine core. The
Network Processor Engine core must perform an explicit write to the specified register
to clear the counter values. There is an overflow bit for each counter to indicate that
the count has “rolled-over.” A mask-able interrupt mechanism is used to enable the
UTOPIA Level-2 coprocessor to flag to the Network Processor Engine core that the “roll
over” has occurred.
19.2 UTOPIA Receive Module
The functionality supported by the Receive Module is tightly coupled with the code
written on the Network Processor Engine core. This section details the full hardware
capabilities of the Receive Module contained within the UTOPIA Level-2 Coprocessor of
the IXP42X product line and IXC1100 control plane processors. The module’s user-
accessible features are described in the Intel
®
IXP400 Software Programmer’s Guide
and may be a subset of the features described in this section.
The UTOPIA Level-2 Receive interface receives ATM cells from one or more UTOPIA-
compliant physical devices.
In multiple-PHY (MPHY) mode, the UTOPIA Level-2 receive interface uses a round-robin
polling routine to poll the various physical interfaces using the five receive address lines
(UTP_RX_ADDR) to determine which physical interfaces are ready to send data. The
result of the polling is provided as status to the Network Processor Engine core. The
Receive Module is the entity within the UTOPIA coprocessor that implements this
functionality.
The Receive Module will poll a programmable number of physical interfaces, as defined
by the Receive Address Range (RXADDRRANGE) register. If three physical interfaces
are connected to the UTOPIA Level-2 interface, a value of two can be programmed into
the Receive Address Range (RXADDRRANGE) register by the Network Processor Engine
core. The polling will always begin at address 0 and poll sequentially to the value
contained in the Receive Address Range (RXADDRRANGE) register. If, for example, a
two was programmed into the Receive Address Range (RXADDRRANGE) register, the
external physical interfaces would have to be configured to respond to the first three
physical addresses produced by the UTOPIA Level-2 UTP_RX_ADDR signals.
To allow the most flexibility a logical address to physical address table is provided. The
look-up table makes it possible for the three addresses that were called out above not
to be in sequential order.
For example, the following logical to physical address map could be used for the above
example of three physical interfaces.
• Logical Address 0 => Physical Address 3 => UTP_RX_ADDR lines = “00011”
• Logical Address 1 => Physical Address 5 => UTP_RX_ADDR lines = “00101”
• Logical Address 2 => Physical Address 7 => UTP_RX_ADDR lines = “00111”
Once the physical address is driven to all physical interfaces using the UTP_RX_ADDR
signals. The physical interface that is prepared to send a cell — and configured to the
address signals that match the values contained on the UTP_RX_ADDR signals —
responds to the UTOPIA Level-2 Interface on the IXP42X product line and IXC1100