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Intel
®
IXP42X product line and IXC1100 control plane processors—SDRAM Controller
Intel
®
IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
DM September 2006
276 Order Number: 252480-006US
7.0 SDRAM Controller
The SDRAM Controller performs data movement between the Intel
®
IXP42X Product
Line of Network Processors and IXC1100 Control Plane Processor and an attached
SDRAM. The SDRAM Controller is a target only function on both AHB interfaces and
supports a maximum of 256 Mbyte of addressable space.
Table 105 shows the supported memory configuration. Support is included for two
memory banks of SDRAM devices. The SDRAM Controller supports a maximum burst
length of eight words. The eight-word burst length was derived from the Intel XScale
®
Processor cache line size. This choice of the eight-word burst size optimizes the
performance of the Intel XScale processor at the same time ensuring fairness among
all resources trying to obtain access to the SDRAM.
The SDRAM Controller can be configured from the South AHB bus only. The SDRAM
controller provides separate interfaces to the South AHB and North AHB to allow for
maximum efficiency of the SDRAM accesses. The SDRAM Controller supports a RAS-to-
CAS delay of three clocks. The SDRAM Controller can be programmed to support a
CAS-to-data delay of two or three clocks. The SDRAM Controller can maintain up to
eight simultaneously open pages.
Two independent chip-selects are provided which allows the SDRAM Controller to
support a total of two physical banks of memory. A minimum of 8Mbyte (using 64Mbit
density chips) to maximum of 256Mbyte (using 512Mbit density chips) memory
configurations are supported.
Figure 53 shows a configuration of SDRAM using only Bank0 of the Intel
®
IXP42X
product line and IXC1100 control plane processors. Bank 0 consists of two SDRAM
devices that are of type by 16 (x16) or 16-bit.