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Intel
®
IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
September 2006 DM
Order Number: 252480-006US 145
Intel XScale
®
Processor—Intel
®
IXP42X product line and IXC1100 control plane processors
3.8.2.2 26-Bit Architecture
The Intel XScale processor does not support 26-bit architecture.
3.8.2.3 Thumb
The Intel XScale processor supports the thumb instruction set.
3.8.2.4 ARM
*
DSP-Enhanced Instruction Set
The Intel XScale
®
Processor implements ARM’s DSP-enhanced instruction set which is a
set of instructions that boost the performance of signal processing applications. There
are new multiply instructions that operate on 16-bit data values and new saturation
instructions. Saturated instructions are used to ensure accuracy during DSP operations
to ensure the signed extension is maintained during an overflow arithmetic operation.
Further information on saturated integer arithmetic can be found in the ARM*
Architecture Reference Manual.
Some of the new instructions are:
• SMLAxy................................................................................. 32<=16x16+32
• SMLAWy ............................................................................... 32<=32x16+32
• SMLALxy ............................................................................... 64<=16x16+64
• SMULxy.......................................................................................32<=16x16
• SMULWy......................................................................................32<=32x16
• QADD ............. Adds two registers and saturates the result if an overflow occurred
• QDADD .....Doubles and saturates one of the input registers then add and saturate
• QSUB........Subtracts two registers and saturates the result if an overflow occurred
• QDSUB Doubles and saturates one of the input registers then subtract and saturate
The Intel XScale processor also implements Load Two words (LDRD), Store Two Words
(STRD) and cache preload (PLD) instructions with the following implementation notes:
• PLD is interpreted as a read operation by the MMU and is ignored by the data
breakpoint unit, i.e., PLD will never generate data breakpoint events.
• PLD to a non-cacheable page performs no action. Also, if the targeted cache line is
already resident, this instruction has no affect.
• Both LDRD and STRD instructions will generate an alignment exception when the
address bits [2:0] = 0b100.
The transfers of two ARM register values to a coprocessor (MCRR) and the transfer of
values from a coprocessor to two ARM registers (MRRC) are only supported on the
IXP42X product line and IXC1100 control plane processors when directed to
coprocessor 0 and are used to access the internal accumulator. See “Internal
Accumulator Access Format” on page 149 for more information. Access to coprocessors
15 and 14 generate an undefined instruction exception.
3.8.2.5 Base Register Update
If a data abort is signalled on a memory instruction that specifies write-back, the
contents of the base register will not be updated. This holds for all load and store
instructions. This behavior matches that of the first generation ARM processor and is
referred to in the ARM V5TE architecture as the Base Restored Abort Model.