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Intel
®
IXP42X product line and IXC1100 control plane processors—Ethernet MAC A
Intel
®
IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
DM September 2006
426 Order Number: 252480-006US
The physical interface clock speed will be divided by the host-side clock speed and then
rounded to the nearest whole number. The value from this calculation will be written to
the Threshold for Internal Clock (THRESH_INTCLK) Register. For the IXP42X product
line and IXC1100 control plane processors, the value contained in the Threshold for
Internal Clock (THRESH_INTCLK) Register must always be set to hexadecimal 0x01.
Failure to do so will result in unpredictable behavior. The value of the Threshold for
Internal Clock (THRESH_INTCLK) Register will be pre-programmed by the Intel-
supplied APIs to the proper value. Manipulation of this value will result in unpredictable
behavior.
The Core Control (CORE_CONTROL) Register was added to allow the Intel XScale
processor to have some control over the Ethernet coprocessor. Configuring bit 4 of the
Core Control (CORE_CONTROL) Register can configure as an input or as an output the
MDC clock.
Setting bit 4 of the Core Control (CORE_CONTROL) Register to logic 1 enables the
IXP42X product line and IXC1100 control plane processors to drive the MDC clock.
Setting bit 4 of the Core Control (CORE_CONTROL) Register to logic 0 enables an
external source to drive the MDC clock. The IXP42X product line and IXC1100 control
plane processors becomes a recipient of that MDC clock.
Configuring bit 3 of the Core Control (CORE_CONTROL) Register can configure the
Transmit Engine to send a JAM sequence if a new packet starts to be received. Setting
bit 3 of the Core Control (CORE_CONTROL) Register to logic 1 enables the IXP42X
product line and IXC1100 control plane processors to send a JAM sequence if a new
packet is receive.
Setting bit 3 of the Core Control (CORE_CONTROL) Register to logic 0 allows the
Transmit Engine to function in normal mode of operation. Configuring bit 2 of the Core
Control (CORE_CONTROL) Register causes the Transmit FIFO to be flushed. Any
packets that are currently in the Transmit FIFO are discarded.
Setting bit 2 of the Core Control (CORE_CONTROL) Register to logic 1 clears the MII
Interface Transmit FIFO. Setting bit 2 of the Core Control (CORE_CONTROL) Register
back to logic 0 allows the Transmit FIFO to resume normal mode of operation.
Configuring bit 1 of the Core Control (CORE_CONTROL) Register causes the Receive
FIFO to be flushed. Any packets that are currently in the Receive FIFO are discarded.
Setting bit 1 of the Core Control (CORE_CONTROL) Register to logic 1 clears the MII
Interface Receive FIFO. Setting bit 1 of the Core Control (CORE_CONTROL) Register
back to logic 0 allows the Receive FIFO to resume normal mode of operation. Bit 0 of
the Core Control (CORE_CONTROL) Register controls the reset state of the Media
Access Controller (MAC) contained within the Ethernet coprocessor.
Setting bit 0 of the Core Control (CORE_CONTROL) Register back to logic 1 causes the
Media Access Controller to be reset. De-assertion (setting bit 0 to logic 0) allows the
Media Access Controller to resume operation in a fully reset state.
This register needs to be manipulated using Intel-supplied APIs. Failure to manipulate
this register with Intel-supplied APIs will result in unpredictable behavior.
The Random-Seed Register is an 8-bit register used to support PHYs that support Auto
MDI/MDI-X detection. The Random-Seed Register value is the value that is used to feed
the Linear-Feedback Shift Register that is used to select which configuration to start
initialization.
The Random-Seed Register needs to be manipulated using Intel-supplied APIs. Failure
to manipulate this could result in unpredictable behavior.