Intel IXP42X Personal Computer User Manual


 
Intel
®
IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
September 2006 DM
Order Number: 252480-006US 347
Universal Asynchronous Receiver Transceiver (UART)—Intel
®
IXP42X product line and IXC1100
control plane processors
10.4.6 Interrupt Identification Register
In order to minimize software overhead during data character transfers, the UART
prioritizes interrupts into four levels and records these in the Interrupt-Identification
Register. The Interrupt-Identification Register (IIR) stores information indicating that a
prioritized interrupt is pending and the source of that interrupt.
Register IER
Bits Name Description
31:8 (Reserved)
7DMAE
DMA Requests Enable:
0 = DMA requests are disabled
1 = DMA requests are enabled
Not Used On the Intel
®
IXP42X product line and IXC1100 control plane
processors
6UUE
UART Unit Enable:
0 = the unit is disabled
1 = the unit is enabled
5NRZE
NRZ coding Enable:
0 = NRZ coding disabled
1 = NRZ coding enabled
Not Used On the Intel
®
IXP42X product line and IXC1100 control plane
processors
4RTOIE
Receiver Time Out Interrupt Enable:
0 = Receiver data Time out interrupt disabled
1 = Receiver data Time out interrupt enabled
3RIE
Modem Interrupt Enable:
0 = Modem Status interrupt disabled
1 = Modem Status interrupt enabled
2RLSE
Receiver Line Status Interrupt Enable:
0 = Receiver Line Status interrupt disabled
1 = Receiver Line Status interrupt enabled
The DLAB bit in the Line Control Register must be set to logic 0 to access this
register.
1TIE
Transmit Data request Interrupt Enable:
0 = Transmit FIFO Data Request interrupt disabled
1 = Transmit FIFO Data Request interrupt enabled
0RAVIE
Receiver Data Available Interrupt Enable:
0 = Receiver Data Available (Trigger level reached) interrupt disabled
1 = Receiver Data Available (Trigger level reached) interrupt enabled
Priority Level Interrupt origin
1
(highest)
Receiver Line Status:
One or more error bits were set.
2
Received Data is available:
In FIFO mode, trigger level was reached.
In non-FIFO mode, RBR has data.