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Intel
®
IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
September 2006 DM
Order Number: 252480-006US 7
—Intel
®
IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
6.3 Initializing PCI Controller Configuration and Status Registers for Data Transactions .. 219
6.3.1 Example: AHB Memory Base Address Register, AHB I/O
Base Address Register, and PCI Memory Base Address
Register .............................................................................................. 220
6.3.2 Example: PCI Memory Base Address Register and South-AHB Translation .... 222
6.4 Initializing the PCI Controller Configuration Registers ........................................... 222
6.5 PCI Controller South AHB Transactions............................................................... 225
6.6 PCI Controller Functioning as Bus Initiator .......................................................... 226
6.6.1 PCI Byte Enables.................................................................................. 226
6.6.2 Initiated Type-0 Read Transaction .......................................................... 227
6.6.3 Initiated Type-0 Write Transaction.......................................................... 227
6.6.4 Initiated Type-1 Read Transaction .......................................................... 228
6.6.5 Initiated Type-1 Write Transaction.......................................................... 229
6.6.6 Initiated Memory Read Transaction......................................................... 229
6.6.7 Initiated Memory Write Transaction ........................................................ 230
6.6.8 Initiated I/O Read Transaction ............................................................... 231
6.6.9 Initiated I/O Write Transaction............................................................... 231
6.6.10 Initiated Burst Memory Read Transaction................................................. 232
6.6.11 Initiated Burst Memory Write Transaction ................................................ 233
6.7 PCI Controller Functioning as Bus Target ............................................................ 234
6.8 PCI Controller DMA Controller ........................................................................... 234
6.8.1 AHB to PCI DMA Channel Operation ........................................................ 238
6.8.2 PCI to AHB DMA Channel Operation ........................................................ 238
6.9 PCI Controller Door Bell Register ....................................................................... 239
6.10 PCI Controller Interrupts .................................................................................. 240
6.10.1 PCI Interrupt Generation ....................................................................... 240
6.10.2 Internal Interrupt Generation................................................................. 240
6.11 PCI Controller Endian Control............................................................................ 241
6.12 PCI Controller Clock and Reset Generation.......................................................... 248
6.13 PCI RCOMP Circuitry ........................................................................................ 249
6.14 Register Descriptions ....................................................................................... 249
6.14.1 PCI Configuration Registers ................................................................... 249
6.14.1.1 Device ID/Vendor ID Register................................................... 250
6.14.1.2 Status Register/Control Register ............................................... 250
6.14.1.3 Class Code/Revision ID Register ............................................... 252
6.14.1.4 BIST/Header Type/Latency Timer/Cache Line Register ................. 252
6.14.1.5 Base Address 0 Register .......................................................... 253
6.14.1.6 Base Address 1 Register .......................................................... 254
6.14.1.7 Base Address 2 Register .......................................................... 254
6.14.1.8 Base Address 3 Register .......................................................... 255
6.14.1.9 Base Address 4 Register .......................................................... 255
6.14.1.10Base Address 5 Register .......................................................... 256
6.14.1.11Subsystem ID/Subsystem Vendor ID Register............................. 256
6.14.1.12Max_Lat, Min_Gnt, Interrupt Pin, and Interrupt Line Register........ 257
6.14.1.13Retry Timeout/TRDY Timeout Register ....................................... 257
6.14.2 PCI Controller Configuration and Status Registers..................................... 258
6.14.2.1 PCI Controller Non-pre-fetch Address Register ............................ 259
6.14.2.2 PCI Controller Non-pre-fetch Command/Byte Enables Register...... 259
6.14.2.3 PCI Controller Non-Pre-fetch Write Data Register ........................ 260
6.14.2.4 PCI Controller Non-Pre-fetch Read Data Register......................... 260
6.14.2.5 PCI Controller Configuration Port Address/Command/
Byte Enables Register.............................................................. 260
6.14.2.6 PCI Controller Configuration Port Write Data Register .................. 261
6.14.2.7 PCI Controller Configuration Port Read Data Register................... 262
6.14.2.8 PCI Controller Control and Status Register ................................. 262
6.14.2.9 PCI Controller Interrupt Status Register ..................................... 263
6.14.2.10PCI Controller Interrupt Enable Register..................................... 264