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Intel
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IXP42X product line and IXC1100 control plane processors—JTAG Interface
Intel
®
IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
DM September 2006
550 Order Number: 252480-006US
Test logic operation is designed such that no disturbance is caused to on-chip system
logic operation as the result of such an error.
20.1.2 Run-Test/Idle State
The TAP controller enters the Run-Test/Idle state between scan operations. The
controller remains in this state as long as the JTG_TMS is held at logic 0. For the
IXP42X product line and IXC1100 control plane processors, the Run-Test/Idle state is
strictly an idle state.
When the JTG_TMS is logic 1 on the rising edge of TCK, the controller moves to the
Select-DR-Scan state.
20.1.3 Select-DR-Scan State
The Select-DR-Scan state is a temporary controller state. The test data registers
selected by the current instruction retain their previous state.
If the JTG_TMS signal is held to logic 0 on the rising edge of JTG_TCK when the
controller is in the Select-DR-Scan state, the controller moves into the Capture-DR
state and a scan sequence — for the selected test data register — is initiated.
If JTG_TMS is held to logic 1 on the rising edge of JTG_TCK, the controller moves into
the Select-IR-Scan state. The instruction does not change while the TAP controller is in
this state.
20.1.4 Capture-DR State
When the controller is in this state and the current instruction is BS_SAMPLE/PRELOAD,
the Boundary-Scan Register captures input pin data on the rising edge of JTG_TCK.
Test data registers that do not have parallel inputs are not changed.
If the BS_SAMPLE/PRELOAD instruction is not selected, while in the Capture-DR state,
the Boundary-Scan registers retain their previous state. In addition, any other data
register under test will place the current value of the selected register into the shift
register connected between JTG_TDI and JTG_TDO.
The instruction does not change while the TAP controller is in the Capture-DR state.
If JTG_TMS is logic 1 on the rising edge of JTG_TCK, the controller enters the Exit1-DR
state. If JTG_TMS is logic 0 on the rising edge of JTG_TCK, the controller enters the
Shift-DR state.
20.1.5 Shift-DR State
In the Shift-DR state, the test data register — which is connected between JTG_TDI
and JTG_TDO as a result of the current instruction — shifts data one bit position nearer
to its serial output on each rising edge of JTG_TCK. At the same time that data is
shifted out, new data for updating the currently selected test register connected
between JTG_TDI and JTG_TDO can be loaded with new data. Passing through the
Update-DR state causes this newly loaded value to be captured by the currently
selected test data register. Test data registers that the current instruction select but do
not place in the serial path, retain their previous value during this state.
The instruction does not change while the TAP controller is in this state.
If JTG_TMS is logic 1 on the rising edge of JTG_TCK, the controller enters the Exit1-DR
state. If JTG_TMS is logic 0 on the rising edge of JTG_TCK, the controller remains in the
Shift-DR state.