Intel IXP42X Personal Computer User Manual


 
Intel
®
IXP42X product line and IXC1100 control plane processors—Ethernet MAC A
Intel
®
IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
DM September 2006
438 Order Number: 252480-006US
15.2.26 Address Mask 2
15.2.27 Address Mask 3
15.2.28 Address Mask 4
15.2.29 Address Mask 5
Register Name: addrmask2
Hex Offset Address: 0x C80090A4 Reset Hex Value: 0x00000000
Register
Description:
Address Mask Register #1. Second register of six that makes up the Address Mask. Address Mask is used
with Address for multicast address filtering. Bits set to 1, in Address Mask, represent bits of the Address
Register that must match the corresponding bits in incoming destination addresses for packets to be
accepted.
Access: Read/Write.
31 87 0
(Reserved) ADDRESS MASK[15:8]
Register Name: addrmask3
Hex Offset Address: 0x C80090A8 Reset Hex Value: 0x00000000
Register
Description:
Address Mask Register #1. Third register of six that makes up the Address Mask. Address Mask is used
with Address for multicast address filtering. Bits set to 1, in Address Mask, represent bits of the Address
Register that must match the corresponding bits in incoming destination addresses for packets to be
accepted.
Access: Read/Write.
31 87 0
(Reserved) ADDRESS MASK [23:16]
Register Name: addrmask4
Hex Offset Address: 0x C80090AC Reset Hex Value: 0x00000000
Register
Description:
Address Mask Register #1. Forth register of six that makes up the Address Mask. Address Mask is used
with Address for multicast address filtering. Bits set to 1 in Address Mask represent bits of the Address
Register that must match the corresponding bits in incoming destination addresses for packets to be
accepted.
Access: Read/Write.
31 87 0
(Reserved) ADDRESS MASK[31:24]
Register Name: addrmask5
Hex Offset Address: 0x C80090B0 Reset Hex Value: 0x00000000
Register
Description:
Address Mask Register #1. Fifth register of six that makes up the Address Mask. Address Mask is used
with Address for multicast address filtering. Bits set to 1 in Address Mask represent bits of the Address
Register that must match the corresponding bits in incoming destination addresses for packets to be
accepted.
Access: Read/Write.
31 87 0
(Reserved) ADDRESS MASK [39:32]