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Intel
®
IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
September 2006 DM
Order Number: 252480-006US 529
Universal Serial Bus (USB) v1.1 Device Controller—Intel
®
IXP42X product line and IXC1100
control plane processors
18.5.31 UDC Data Register 1 (UDDR1)
Endpoint 1 is a double-buffered bulk IN endpoint that is 64 bytes deep. Data can be
loaded via direct Intel XScale
®
processor writes. Because it is double-buffered, up to
two packets of data may be loaded for transmission.
18.5.32 UDC Data Register 2 (UDDR2)
Endpoint 2 is a double-buffered bulk OUT endpoint that is 64 bytes deep. The UDC will
generate an interrupt as soon as the EOP is received.
Register Name: UDDR0
Hex Offset Address: 0 x C800B080 Reset Hex Value: 0x00000000
Register
Description:
Universal Serial Bus Device Endpoint 0 Data Register
Access: Read/Write
Bits
31 80
(Reserved) (Data)
X
Resets (Above)
Register
UDDR0
Bits Name Description Read Access Write Access
31:8 Reserved for future use.
7:0 DATA
Top/bottom of endpoint 0 FIFO data.
Read Bottom of endpoint 0 FIFO data.
Write Top of endpoint 0 FIFO data.
Bottom of
Endpoint 0 FIFO
Top of Endpoint
0 FIFO
Register Name: UDDR1
Hex Offset Address: 0 x C800B100 Reset Hex Value: 0x00000000
Register
Description:
Universal Serial Bus Device Endpoint 1 Data Register
Access: Write
Bits
31 876543210
(Reserved) (8-Bit Data)
X 00000000
Resets (Above)
Register
UDDR1
Bits Name Description
31:8 Reserved for future use.
7:0 DATA Top of endpoint data currently being loaded.