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Intel
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IXP42X product line and IXC1100 control plane processors—Introduction
Intel
®
IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
DM September 2006
28 Order Number: 252480-006US
LSB Least-Significant Byte
LUT Look-Up Table
MAC Media Access Controller
MDIO Management Data Input/Output
MIB Management Information Base
MII Media-Independent Interface
MMU Memory Management Unit
MSb Most-Significant bit
MSB Most-Significant Byte
MVIP Multi-Vendor Integration Protocol
NPE Network Processor Engine
NRZI Non-Return To Zero Inverted
PCI Peripheral Component Interconnect
PEC Programmable Event Counters
PHY Physical Layer (Layer 1) Interface
Reserved
A field that may be used by an implementation. Software should not modify reserved
fields or depend on any values in reserved fields.
RX Receive (HSS is receiving from off-chip)
SFD Start of Frame Delimiter
SRAM Static Random Access Memory
SDRAM Synchronous Dynamic Random Access Memory
T1 Type 1 trunk line
TDM Time Division Multiplex
TLB Translation Look-Aside Buffer
TX Transmit (HSS is transmitting off-chip)
UART Universal Asynchronous Receiver-Transmitter
WAN Wide Area Network
Table 1. Acronyms and Terminology (Continued)
Acronym/
Terminology
Description