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Intel
®
IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
September 2006 DM
Order Number: 252480-006US 265
PCI Controller—Intel
®
IXP42X product line and IXC1100 control plane processors
6.14.2.11 DMA Control Register
(PCI_DMACTRL)
Register Name: PCI_DMACTRL
Hex Offset Address: 0xC0000028 Reset Hex Value: 0x00000000
Register
Description:
Control and status for the DMA Controller channels.
Access: See below.
31 161514131211 9876543 10
(Reserved)
PADE1
PADC1
PADE0
PADC0
(Rsvd)
PADCEN
APDE1
APDC1
APDE0
APDC0
(Rsvd)
APDCEN
Register PCI_DMACTRL (Sheet 1 of 2)
Bits Name Description
Reset
Value
PCI Access AHB Access
31:1
6
(Reserved) – Read as 0 0x0000 RO RO
15 PADE1
PCI to AHB DMA error for buffer 1. Set to a 1 when
the DMA transfer specified by the pci_ptadma1_xxx
registers terminates due to an error. Read-only,
cleared when a 1 is written to the PADC1 bit.
0RORO
14 PADC1
PCI to AHB DMA complete for buffer 1. Set to a 1
when the DMA transfer specified by the
pci_ptadma1_xxx registers is complete or terminated
due to an error. If the PADCEN bit is a 1, the
pcc_ptadma_int output is asserted.
0RORW1C
13 PADE0
PCI to AHB DMA error for buffer 0. Set to a 1 when
the DMA transfer specified by the pci_ptadma0_xxx
registers terminates due to an error. Read-only,
cleared when a 1 is written to the PADC0 bit.
0RORO
12 PADC0
PCI to AHB DMA complete for buffer 0. Set to a 1
when the DMA transfer specified by the
pci_ptadma0_xxx registers is complete or terminated
due to an error. If the PADCEN bit is a 1, the
pcc_ptadma_int output is asserted.
0RORW1C
11:9 (Reserved) – Read as 0 000 RO RO
8 PADCEN
PCI to AHB DMA Complete interrupt enable. If this bit
is set and either PADC0 or PADC1 are 1, the
pcc_ptadma_int output is asserted.
0RORW
7APDE1
AHB to PCI DMA error for buffer 1. Set to a 1 when
the DMA transfer specified by the pci_atpdma1_xxx
registers terminates due to an error. Read-only,
cleared when a 1 is written to the APDC1 bit.
0RORO
6APDC1
AHB to PCI DMA complete for buffer 1. Set to a 1
when the DMA transfer specified by the
pci_atpdma1_xxx registers is complete or terminated
due to an error. If the APDCEN bit is a 1, the
pcc_atpdma_int output is asserted.
0RORW1C
5APDE0
AHB to PCI DMA error for buffer 0. Set to a 1 when
the DMA transfer specified by the pci_atpdma0_xxx
registers terminates due to an error. Read-only,
cleared when a 1 is written to the APDC0 bit.
0RORO