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Intel
®
IXP42X product line and IXC1100 control plane processors—Timers
Intel
®
IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
DM September 2006
408 Order Number: 252480-006US
14.0 Timers
The Intel
®
IXP42X Product Line of Network Processors and IXC1100 Control Plane
Processor contain four 32-bit internal timers that increment on the rising edge of a
66.66 MHz (which is 2* OSC_IN input pin.). The watch-dog timer is a 32-bit, down
counter that may be used by software applications to monitor inactivity. The time-
stamp counter is a 32-bit, free-running, up counter that may be used by software
applications to maintain a real time count or apply time stamps to events.
The two general-purpose counters are 32-bit counters that may be used by software
applications to generate periodic interrupts to the Intel
®
IXP42X product line and
IXC1100 control plane processors’ Interrupt Controller. The general-purpose timer
interrupts sent to the Interrupt Controller will allow software application, running on
the Intel XScale
®
processor, to aid in the implementation of system-level traffic-
shaping algorithms. Alternately, they can be used as an operating-system timer.
All read and write accesses to the timers must be made as 32-bit accesses. Bits that
correspond to reserved register bits are ignored on writes. These same reserved
register bits will be returned as zeros on read accesses.
14.1 Watch-Dog Timer
The watch-dog timer is composed of a 32-bit writeable down counter, a 3-bit enable
register, a 16-bit key register, and a 5-bit status register. The watch-dog timer can only
be written or read by utilizing the APB bus. The Watch-Dog Timer Key Register
(ost_wdog_key) can be written at any time over the APB bus. However, the Watch-Dog
Timer Down Counter (ost_wdog) and the Watch-Dog Enable Register (ost_wdog_enab)
can only be written when the Watch-Dog Timer Key Register contains the value
0x482E.
Note: The value 0x482E will be referred to as the “key-value” from here on.
A write to the Watch-Dog Timer Down Counter and the Watch-Dog Timer Enable
Register when the Watch-Dog Timer Key Register does not equal the key-value will
have no effect on the Watch-Dog Timer Down Counter or the Watch-Dog Timer Enable
Register. The Watch-Dog Timer Key Register is provided to prevent accidental writes to
the Watch-Dog Timer Down Counter Register and the Watch-Dog Timer Enable
Register. Typical operation of the Watch-Dog Counter would be for the software
application to write the key-value into the Watch-Dog Timer Key Register, write to the
Watch-Dog Timer Down Counter or the Watch-Dog Timer Enable Register, then write a
value other than key-value into the Watch-Dog Timer Key Register. The software
application will periodically write the key-value repeat the above process to prevent the
Watch-Dog Timer Down Counter from reaching zero.
The watch-dog enable register contains 3-bits. The 3-bits are the watch-dog counter
enable bit, the watch-dog interrupt enable bit, and the watch-dog reset enable bit. The
watch-dog counter enable bit enables and disables the Watch-Dog Timer Down Counter
register. When the watch-dog counter enable bit is set to logic 1, the Watch-Dog Timer
Down Counter will decrement. When the watch-dog counter enable bit is set to logic 0
the watch-dog counter down counter will halt.