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Intel
®
IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
September 2006 DM
Order Number: 252480-006US 273
PCI Controller—Intel
®
IXP42X product line and IXC1100 control plane processors
6.14.2.27 PCI to AHB DMA PCI Address Register 1
(PCI_PTADMA1_PCIADDR)
6.14.2.28 PCI to AHB DMA Length Register 1
(PCI_PTADMA1_LENGTH)
Register PCI_PTADMA1_AHBADDR
Bits Name Description
Reset
Value
PCI Access AHB Access
31:2 Address AHB word address 0x00000000 RO RW
1:0 Lower AHB address bits hard-wired to zero. 00 RO RO
Register Name: PCI_PTADMA1_PCIADDR
Hex Offset Address: 0xC0000068 Reset Hex Value: 0x00000000
Register
Description:
Source address on the PCI bus for PCI to AHB DMA transfers. Paired with pci_ptadma0_pciaddr to allow
buffering of DMA transfer requests.
Access: See below.
31 210
address 0 0
Register
PCI_PTADMA1_PCIADDR
Bits Name Description
Reset
Value
PCI Access AHB Access
31:2 Address PCI word address 0x00000000 RO RW
1:0 Lower PCI address bits hard-wired to zero. 00 RO RO
Register Name: PCI_PTADMA1_LENGTH
Hex Offset Address: 0xC000006C Reset Hex Value: 0x00000000
Register
Description:
Provides word count and control for PCI to AHB DMA transfers. Paired with pci_ptadma0_length to allow
buffering of DMA transfer requests.
Access: See below.
31 30 29 28 27 16 15 0
EN
(Rsvd)
BE
(Reserved) wordcount
Register
PCI_PTADMA1_LENGTH (Sheet 1 of 2)
Bits Name Description
Reset
Value
PCI Access AHB Access
31 EN
Channel enable. When set to a 1, executes a DMA
transfer if wordcount is nonzero. When 0, the channel
is disabled. Hardware clears this bit when the DMA
transfer is complete.
0RORW
30:2
9
(Reserved). Read as 0. 00 RO RO