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Intel
®
IXP42X product line and IXC1100 control plane processors—Universal Serial Bus (USB)
v1.1 Device Controller
Intel
®
IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
DM September 2006
510 Order Number: 252480-006US
18.5.15 UDC Endpoint 13 Control/Status Register (UDCCS13)
The UDC Endpoint 13 Control Status Register contains four bits that are used to
operate endpoint 13, an Isochronous IN endpoint.
18.5.15.1 Transmit FIFO Service (TFS)
The transmit FIFO service bit is be set if one or fewer data packets remain in the
transmit FIFO. UDCCS13[TFS] is cleared when two complete data packets are in the
FIFO. A complete packet of data is signified by loading 256 bytes or by setting
UDCCS13[TSP].
18.5.15.2 Transmit Packet Complete (TPC)
The the UDC sets transmit packet complete bit when an entire packet is sent to the
host. When this bit is set, the IR13 bit in the appropriate UDC status/interrupt register
is set if transmit interrupts are enabled.
This bit can be used to validate the other status/error bits in the endpoint 13 Control/
Status Register. The UDCCS13[TPC] bit gets cleared by writing a 1 to it. This clears the
interrupt source for the IR13 bit in the appropriate UDC status/interrupt register, but
the IR13 bit must also be cleared.
Setting this bit does not prevent the UDC from transmitting the next buffer. The UDC
issues NAK handshakes to all IN tokens if this bit is set and neither buffer has been
triggered by writing 64 bytes or setting UDCCS13[TSP].
18.5.15.3 Flush Tx FIFO (FTF)
The Flush Tx FIFO bit triggers a reset for the endpoint's transmit FIFO. The Flush Tx
FIFO bit is set when software writes a 1 to it or when the host performs a
SET_CONFIGURATION or SET_INTERFACE.
Register UDCCS12
Bits Name Description
31:8 Reserved for future use.
7RSP
Receive short packet (read only).
1 = Short packet received and ready for reading.
6RNE
Receive FIFO not empty (read-only).
0 = Receive FIFO empty.
1 = Receive FIFO not empty.
5FST
Force stall (read/write).
1 = Issue STALL handshakes to OUT tokens.
4SST
Sent stall (read/write 1 to clear).
1 = STALL handshake was sent.
3(Reserved)
2 (Reserved). Always reads zero.
1RPC
Receive packet complete (read/write 1 to clear).
0 = Error/status bits invalid.
1 = Receive packet has been received and error/status bits are valid.
0RFS
Receive FIFO service (read-only).
0 = Receive FIFO has less than 1 data packet.
1 = Receive FIFO has 1 or more data packets.