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Intel
®
IXP42X product line and IXC1100 control plane processors—Internal Bus
Intel
®
IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
DM September 2006
204 Order Number: 252480-006US
5.0 Internal Bus
The internal bus architecture of the Intel
®
IXP42X Product Line of Network Processors
and IXC1100 Control Plane Processor are designed to allow parallel processing to occur
and isolate bus utilization based upon particular traffic patterns. The bus is segmented
into three major buses, the North AHB, the South AHB, and the APB.
The North AHB is a 133-MHz, 32-bit bus that can be mastered by the WAN/Voice
Network Processor Engine (NPE), Ethernet NPE A, or Ethernet NPE B. The targets of the
North AHB can be the SDRAM or the AHB/AHB Bridge. The AHB/AHB Bridge will allow
access by the NPEs to the peripherals and internal targets on the South AHB.
Data transfers by the NPEs from the North AHB to the South AHB are targeted
predominately to the queue manager. Transfers to the AHB/AHB Bridge may be
“posted” when writing or “split” when reading — allowing control of the North AHB to
be given to another master on the North AHB and allowing the bus to achieve
maximum efficiency.
Transfers to the AHB/AHB Bridge are considered to be small and infrequent, relative to
the traffic passed between the NPEs on the North AHB and the SDRAM.
The South AHB is a 133-MHz, 32-bit bus that can be mastered by the Intel XScale
®
Processor, PCI Controller, and the AHB/AHB Bridge. The targets of the South AHB can
be the SDRAM, PCI Controller, Queue Manager, Expansion Bus Controller, or the AHB/
APB Bridge. Accessing across the AHB/APB Bridge allows interfacing to peripherals
attached to the APB Bus.
The APB is a 66.66 MHz (which is 2 * OSC_IN input pin.) (32-bit bus that can be
mastered by the AHB/APB Bridge only. The targets of the APB can be the High-Speed
UART Interface, Console UART Interface, USB v 1.1 interface, all NPEs, the Internal Bus
Performance Monitoring Unit (PMU), Interrupt Controller, GPIO, and Timers. The APB
interface to the NPEs is used for NPE code download, part configuration, and status
collection.
The maximum length that any AHB master can hold the AHB is for eight 32-bit words.
This feature allows for fairness among all masters on the AHBs.
5.1 Internal Bus Arbiters
The Intel
®
IXP42X product line and IXC1100 control plane processors contain two
internal bus arbiters, one arbiter for North AHB transactions and one arbiter for South
AHB transactions. The arbiters are used to ensure that at any particular time only one
AHB master has access to a given AHB. The arbiters perform this function by observing
all of the AHB master requests to the given AHB segment and deciding which AHB
master will be the next owner of the AHB.
The arbiters have a standard interface to all bus masters and split-capable slaves in the
system. Any AHB master can request an AHB at any cycle. The arbiters sample the AHB
requests. If the particular AHB master is requesting the AHB and is next in the round
robin list, the arbiter will grant the Master the AHB.