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Intel
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IXP42X product line and IXC1100 control plane processors—Ethernet MAC A
Intel
®
IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
DM September 2006
432 Order Number: 252480-006US
15.2.9 Transmit Deferral Parameters
15.2.10 Receive Deferral Parameters
Register txbuffsize
Bits Name Description
31:8 (Reserved)
7:0
Tx Buffer
size
Holds minimum number of bytes of each frame that must be in the Transmit
FIFO for that frame's transmission to start.
If a complete frame is less than this minimum, it is always transmitted.
Register Name: txdefpars
Hex Offset Address: 0xC8009050 Reset Hex Value: 0x00000000
Register
Description:
Transmit Deferral Parameters Register
Access: Read/Write.
31 87 0
(Reserved) Receive Deferral
Register txdefpars
Bits Name Description
31:8 (Reserved)
7:0
Transmit
Deferral
Number of transmit clock cycles (tx_clk) in the transmit deferral period minus
three, when single deferral is used for transmission (Transmit Control[15] = 0).
Register Name: rxdefpars
Hex Offset Address: 0xC8009054 Reset Hex Value: 0x00000000
Register
Description:
Receive Deferral Parameters Register
Access: Read/Write.
31 87 0
(Reserved) Receive Deferral
Register rxdefpars
Bits Name Description
31:8 (Reserved)
7:0
Receive
Deferral
Number of receive clock cycles (rx_clk) in the receive deferral period minus
three, when checking the Inter Frame Gap for packets received (Receive Control
2[0] = 0).